| /external/llvm/test/CodeGen/Thumb2/ |
| thumb2-orn.ll | 9 ; CHECK: orn r0, r0, r1
17 ; CHECK: orn r0, r0, r1
25 ; CHECK: orn r0, r0, r1
33 ; CHECK: orn r0, r0, r1
42 ; CHECK: orn r0, r0, r1, lsl #5
51 ; CHECK: orn r0, r0, r1, lsr #6
60 ; CHECK: orn r0, r0, r1, asr #7
71 ; CHECK: orn r0, r0, r0, ror #8
|
| thumb2-orn2.ll | 10 ; CHECK: orn r0, r0, #187
19 ; CHECK: orn r0, r0, #11141290
28 ; CHECK: orn r0, r0, #-872363008
37 ; CHECK: orn r0, r0, #1114112
|
| /external/llvm/test/MC/AArch64/ |
| alias-logicalimm.s | 26 orn x0, x1, #2
31 orn w2, w1, #3
|
| arm64-logical-encoding.s | 204 orn w1, w2, w3
205 orn x1, x2, x3
206 orn w1, w2, w3, lsl #7
207 orn x1, x2, x3, lsl #7
208 orn w1, w2, w3, lsr #7
209 orn x1, x2, x3, lsr #7
210 orn w1, w2, w3, asr #7
211 orn x1, x2, x3, asr #7
212 orn w1, w2, w3, ror #7
213 orn x1, x2, x3, ror #
[all...] |
| neon-bitwise-instructions.s | 45 orn v0.8b, v1.8b, v2.8b
46 orn v0.16b, v1.16b, v2.16b
56 // CHECK: orn v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0xe2,0x0e]
57 // CHECK: orn v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0xe2,0x4e]
|
| /external/clang/test/CodeGen/ |
| aarch64-neon-3v.c | 395 // CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
401 // CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
407 // CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
413 // CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
419 // CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
425 // CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
431 // CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
437 // CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
443 // CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
449 // CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16
[all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-logical.txt | 214 # CHECK: orn w1, w2, w3
215 # CHECK: orn x1, x2, x3
216 # CHECK: orn w1, w2, w3, lsl #7
217 # CHECK: orn x1, x2, x3, lsl #7
218 # CHECK: orn w1, w2, w3, lsr #7
219 # CHECK: orn x1, x2, x3, lsr #7
220 # CHECK: orn w1, w2, w3, asr #7
221 # CHECK: orn x1, x2, x3, asr #7
222 # CHECK: orn w1, w2, w3, ror #7
223 # CHECK: orn x1, x2, x3, ror #
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| logical_shifted_reg.ll | 14 ; First check basic and/bic/or/orn/eor/eon patterns with no shift
28 ; CHECK: orn {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
53 ; CHECK: orn {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
78 ; CHECK: orn {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #1
104 ; First check basic and/bic/or/orn/eor/eon patterns with no shift
118 ; CHECK: orn {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
143 ; CHECK: orn {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
168 ; CHECK: orn {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #1
|
| neon-bitwise-instructions.ll | 67 ; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
75 ; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
472 ; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
480 ; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
488 ; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
496 ; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
504 ; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
512 ; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
[all...] |
| /external/llvm/test/CodeGen/Generic/ |
| 2003-07-08-BadCastToBool.ll | 10 ;; (2) (A or NOT(B)) was being folded into A orn B, which is ok
|
| /system/core/libpixelflinger/tests/arch-arm64/disassembler/ |
| arm64_diassembler_test.cpp | 75 { 0x2a3e0200, "orn w0, w16, w30, lsl #0" },
76 { 0x2a707fdf, "orn wzr, w30, w16, lsr #31" },
77 { 0x2aa043f0, "orn w16, wzr, w0, asr #16" },
78 { 0x2aff401e, "orn w30, w0, wzr, ror #16" },
|
| /external/llvm/test/MC/Sparc/ |
| sparc-alu-instructions.s | 31 ! CHECK: orn %g1, %g2, %g3 ! encoding: [0x86,0x30,0x40,0x02]
32 orn %g1, %g2, %g3
|
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-arm64.cc | 657 COMPARE(orn(w11, w12, Operand(0x40004000)),
659 COMPARE(orn(x13, x14, Operand(0x8181818181818181L)),
717 COMPARE(orn(w15, w16, Operand(w17)), "orn w15, w16, w17");
718 COMPARE(orn(x18, x19, Operand(x20, LSL, 13)), "orn x18, x19, x20, lsl #13");
719 COMPARE(orn(w21, w22, Operand(w23, LSR, 14)), "orn w21, w22, w23, lsr #14");
720 COMPARE(orn(x24, x25, Operand(x26, ASR, 15)), "orn x24, x25, x26, asr #15")
[all...] |
| test-assembler-arm64.cc | 604 TEST(orn) {
612 __ Orn(x2, x0, Operand(x1));
613 __ Orn(w3, w0, Operand(w1, LSL, 4));
614 __ Orn(x4, x0, Operand(x1, LSL, 4));
615 __ Orn(x5, x0, Operand(x1, LSR, 1));
616 __ Orn(w6, w0, Operand(w1, ASR, 1));
617 __ Orn(x7, x0, Operand(x1, ASR, 1));
618 __ Orn(w8, w0, Operand(w1, ROR, 16));
619 __ Orn(x9, x0, Operand(x1, ROR, 16));
620 __ Orn(w10, w0, Operand(0xffff))
[all...] |
| /external/vixl/test/ |
| test-disasm-a64.cc | 627 COMPARE(orn(w11, w12, Operand(0x40004000)),
629 COMPARE(orn(x13, x14, Operand(0x8181818181818181)),
687 COMPARE(orn(w15, w16, Operand(w17)), "orn w15, w16, w17");
688 COMPARE(orn(x18, x19, Operand(x20, LSL, 13)), "orn x18, x19, x20, lsl #13");
689 COMPARE(orn(w21, w22, Operand(w23, LSR, 14)), "orn w21, w22, w23, lsr #14");
690 COMPARE(orn(x24, x25, Operand(x26, ASR, 15)), "orn x24, x25, x26, asr #15")
[all...] |
| test-assembler-a64.cc | 568 TEST(orn) {
575 __ Orn(x2, x0, Operand(x1));
576 __ Orn(w3, w0, Operand(w1, LSL, 4));
577 __ Orn(x4, x0, Operand(x1, LSL, 4));
578 __ Orn(x5, x0, Operand(x1, LSR, 1));
579 __ Orn(w6, w0, Operand(w1, ASR, 1));
580 __ Orn(x7, x0, Operand(x1, ASR, 1));
581 __ Orn(w8, w0, Operand(w1, ROR, 16));
582 __ Orn(x9, x0, Operand(x1, ROR, 16));
583 __ Orn(w10, w0, 0x0000ffff)
[all...] |
| /external/llvm/test/MC/Disassembler/Sparc/ |
| sparc.txt | 36 # CHECK: orn %g1, %g2, %g3
|
| /external/valgrind/main/none/tests/arm/ |
| v6intThumb.stdout.exp | [all...] |
| /external/chromium_org/v8/src/arm64/ |
| constants-arm64.h | 501 ORN = ORR | NOT,
537 ORN_w = LogicalShiftedFixed | ORN,
538 ORN_x = LogicalShiftedFixed | ORN | SixtyFourBits,
[all...] |
| /external/vixl/src/a64/ |
| constants-a64.h | 393 ORN = ORR | NOT,
429 ORN_w = LogicalShiftedFixed | ORN,
430 ORN_x = LogicalShiftedFixed | ORN | SixtyFourBits,
[all...] |
| macro-assembler-a64.cc | 96 void MacroAssembler::Orn(const Register& rd,
100 LogicalMacro(rd, rn, operand, ORN);
223 // could also be achieved using an orr instruction (like orn used by Mvn),
266 // assembler directly, using orn.
[all...] |
| assembler-a64.cc | 679 void Assembler::orn(const Register& rd, function in class:vixl::Assembler
682 Logical(rd, rn, operand, ORN);
1181 orn(rd, AppropriateZeroRegFor(rd), operand);
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| Arm64Disassembler.cpp | 51 {0xff200000, 0x2a200000, "orn <wd>, <wn>, <wm>, <shift2> #<amt1>"},
|
| /external/vixl/doc/ |
| supported-instructions.md | 651 ### orn ###
655 void orn(const Register& rd, const Register& rn, const Operand& operand)
|
| /packages/inputmethods/LatinIME/java/res/values-is-rIS/ |
| strings-letter-descriptions.xml | 62 <string name="spoken_accented_letter_00FE" msgid="8788160115017853040">"Þorn"</string>
|
