| /external/llvm/test/CodeGen/X86/ |
| 2006-01-19-ISelFoldingBug.ll | 2 ; RUN: grep shld | count 1
4 ; Check that the isel does not fold the shld, which already folds a load
|
| shift-coalesce.ll | 2 ; RUN: grep "shld.*cl"
|
| x86-64-double-shifts-Oz-Os-O2.ll | 4 ; Verify that we generate shld insruction when we are optimizing for size,
26 ; Verify that we generate shld insruction when we are optimizing for size,
47 ; Verify that we do not generate shld insruction when we are not optimizing
|
| x86-64-double-shifts-var.ll | 20 ; double precision shift instructions we do not generate 'shld' or 'shrd'
30 ; CHECK-NOT: shld
|
| x86-64-double-precision-shift-left.ll | 4 ; of instructions with lower latencies instead of shld instruction.
|
| rot64.ll | 4 ; RUN: grep shld %t | count 2
|
| /external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/x86/tests/ |
| genopcode.asm | 95 shld ax, bx, 5 label
97 shld ecx, edx, 10 label
98 shld eax, ebx, cl label
|
| /external/linux-tools-perf/perf-3.12.0/arch/sh/lib/ |
| memset-sh4.S | 62 shld r0,r2 ! number of loops
|
| /external/flac/libFLAC/ia32/ |
| bitreader_asm.nasm | 407 shld edi, edx, cl
422 shld edi, edx, cl
485 shld edi, eax, cl
505 shld edi, eax, cl
529 shld edi, eax, cl ; uval <<= parameter <<< 'parameter' bits of tail word
|
| /external/llvm/test/MC/X86/ |
| intel-syntax.s | 377 shld DX, BX label
378 shld DX, BX, CL label
379 shld DX, BX, 1 label
380 shld [RAX], BX label
381 shld [RAX], BX, CL label
|
| x86-64.s | 357 shld %bx, %dx label
358 shld %cl, %bx, %dx label
359 shld $1, %bx, %dx label
360 shld %bx, (%rax) label
361 shld %cl, %bx, (%rax) label
|
| /external/llvm/lib/Target/X86/ |
| X86InstrShiftRotate.td | [all...] |
| X86.td | 80 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
81 "SHLD instruction is slow">;
|
| X86Subtarget.h | 151 /// IsSHLDSlow - True if SHLD instructions are slow.
|
| X86InstrInfo.td | 128 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
[all...] |
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-x87.cc | 122 __ shld(edx, ecx);
201 __ shld(edx, Operand(ebx, ecx, times_4, 10000));
|
| test-disasm-ia32.cc | 122 __ shld(edx, ecx);
201 __ shld(edx, Operand(ebx, ecx, times_4, 10000));
|
| test-disasm-x64.cc | 118 __ shld(rdx, rcx);
192 __ shld(rdx, rbx);
|
| /external/chromium_org/v8/src/x87/ |
| assembler-x87.h | 713 void shld(Register dst, Register src) { shld(dst, Operand(src)); }
714 void shld(Register dst, const Operand& src);
[all...] |
| /external/valgrind/main/docs/internals/ |
| 3_1_BUGSTATUS.txt | 68 vx1615 fixed 126583 amd64->IR: 0x48 0xF 0xA4 0xC2 (shld $1,%rax,%rdx)
|
| /external/chromium_org/third_party/mesa/src/src/mesa/x86/ |
| assyntax.h | 648 #define SHLD_L(a,b,c) CHOICE(shldl ARG3(a,b,c), shldl ARG3(a,b,c), _LTOG shld ARG3(c,b,a))
649 #define SHLD2_L(a,b) CHOICE(shldl ARG2(a,b), shldl ARG3(CL,a,b), _LTOG shld ARG3(b,a,CL))
650 #define SHLD_W(a,b,c) CHOICE(shldw ARG3(a,b,c), shldw ARG3(a,b,c), _WTOG shld ARG3(c,b,a))
651 #define SHLD2_W(a,b) CHOICE(shldw ARG2(a,b), shldw ARG3(CL,a,b), _WTOG shld ARG3(b,a,CL))
[all...] |
| /external/mesa3d/src/mesa/x86/ |
| assyntax.h | 648 #define SHLD_L(a,b,c) CHOICE(shldl ARG3(a,b,c), shldl ARG3(a,b,c), _LTOG shld ARG3(c,b,a))
649 #define SHLD2_L(a,b) CHOICE(shldl ARG2(a,b), shldl ARG3(CL,a,b), _LTOG shld ARG3(b,a,CL))
650 #define SHLD_W(a,b,c) CHOICE(shldw ARG3(a,b,c), shldw ARG3(a,b,c), _WTOG shld ARG3(c,b,a))
651 #define SHLD2_W(a,b) CHOICE(shldw ARG2(a,b), shldw ARG3(CL,a,b), _WTOG shld ARG3(b,a,CL))
[all...] |
| /external/chromium_org/v8/src/ia32/ |
| assembler-ia32.h | 730 void shld(Register dst, Register src) { shld(dst, Operand(src)); }
731 void shld(Register dst, const Operand& src);
[all...] |
| /art/compiler/utils/x86/ |
| assembler_x86.h | 405 void shld(Register dst, Register src);
|
| /external/qemu/distrib/sdl-1.2.15/src/stdlib/ |
| SDL_stdlib.c | 580 shld edx,eax,cl
|
