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  /external/valgrind/main/none/tests/ppc32/
jm-insns.c 6250 volatile vector unsigned int vec_in, vec_out, vscr; local
6309 volatile vector unsigned int vec_in1, vec_in2, vec_out, vscr; local
6375 volatile vector unsigned int vec_in1, vec_in2, vec_in3, vec_out, vscr; local
6450 volatile vector unsigned int vec_in1, vec_out, vscr; local
6520 volatile vector unsigned int vec_in1, vec_out, vscr; local
6590 volatile vector unsigned int vec_out, vscr; local
6648 volatile vector unsigned int vec_in1, vec_in2, vec_out, vscr; local
6723 volatile vector unsigned int vec_out, vscr; local
6833 volatile vector unsigned int vec_in, vec_out, vscr; local
6917 volatile vector unsigned int vec_in, vec_out, vscr; local
6998 volatile vector unsigned int vscr; local
7066 volatile vector unsigned int vscr; local
7133 volatile vector unsigned int vscr; local
7239 volatile vector unsigned int vec_in, vec_out, vscr; local
    [all...]
  /external/libunwind/src/ppc64/
regname.c 146 [UNW_PPC64_VSCR]="VSCR",
ucontext_i.h 170 #define UC_MCONTEXT_VREGS_VSCR ((void *)&dmy_vrregset.vscr - (void *)&dmy_vrregset)
  /external/qemu/gdb-xml/
power-altivec.xml 55 <reg name="vscr" bitsize="32" group="vector"/>
  /external/valgrind/main/coregrind/m_gdbserver/
power-altivec.xml 55 <reg name="vscr" bitsize="32" group="vector"/>
valgrind-low-ppc32.c 148 { "vscr", 7456, 32 },
valgrind-low-ppc64.c 145 { "vscr", 8672, 32 },
  /external/elfutils/0.153/backends/
ppc_corenote.c 78 /* vscr XXX 67 is an unofficial assignment */
ppc_regs.c 104 return stpcpy (name, "vscr") + 1 - name;
ChangeLog 207 * ppc_regs.c (ppc_register_info): Assign 67 to "vscr".
208 Return "vector" and 32 bits for vscr and vrsave.
  /external/lldb/tools/debugserver/source/MacOSX/ppc/
DNBArchImpl.cpp 384 { "vscr" , Uint, 16, Hex },
500 if (reg < 33) // FP0 - FP31 and VSCR
  /external/valgrind/main/coregrind/m_dispatch/
dispatch-ppc32-linux.S 254 VSCR or FPSCR in ways we don't expect. */
280 /* Check VSCR[NJ] == 1 */
285 /* retrieve VSCR and mask wanted bits */
dispatch-ppc64-linux.S 258 VSCR or FPSCR in ways we don't expect. */
275 /* Check VSCR[NJ] == 1 */
280 /* retrieve VSCR and mask wanted bits */
  /external/valgrind/main/include/vki/
vki-ppc64-linux.h 272 #define VKI_ELF_NVRREG 34 /* includes vscr & vrsave in split vectors */
285 * The entry with index 32 contains the vscr as the last word (offset 12)
286 * within the quadword. This allows the vscr to be stored as either a
297 * vrsave along with vscr and so only uses 33 vectors for the register set
328 * index 32 contains the vscr as the last word (offset 12) within the
329 * quadword. This allows the vscr to be stored as either a quadword (since
vki-ppc32-linux.h 726 #define VKI_ELF_NVRREG 33 /* includes vscr */
    [all...]
  /external/llvm/include/llvm/IR/
IntrinsicsPowerPC.td 115 // VSCR access.
  /external/libunwind/src/ptrace/
_UPT_reg_offset.c 442 [UNW_PPC64_VSCR] = UNW_PPC_PT(VSCR), \
  /external/chromium_org/third_party/WebKit/Source/core/html/parser/
HTMLEntityNames.in 583 "Vscr;","U+1D4B1"
    [all...]
  /external/tagsoup/src/org/ccil/cowan/tagsoup/
HTMLSchema.java     [all...]
  /external/valgrind/main/memcheck/
mc_machine.c 216 if (o == GOF(VSCR) && sz == 4) return -1;
417 if (o == GOF(VSCR) && sz == 4) return -1;
    [all...]
  /external/tagsoup/definitions/
html.tssl     [all...]
  /external/clang/lib/CodeGen/
TargetInfo.cpp     [all...]
  /external/owasp/sanitizer/lib/htmlparser-1.3/doc/
named-character-references.html     [all...]
  /external/valgrind/main/VEX/priv/
guest_ppc_toIR.c     [all...]
  /external/clang/lib/Basic/
Targets.cpp     [all...]

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