Lines Matching refs:rd
420 // ldr rd, [pc, #offset]
423 // ldr rd, [pp, #offset]
452 // A mask for the Rd register for push, pop, ldr, str instructions.
675 // ldr<cond> <Rd>, [pc +/- offset_12].
682 // ldr<cond> <Rd>, [pp +/- offset_12].
1068 rd,
1077 Register target = rd.code() == pc.code() ? ip : rd;
1088 if (target.code() != rd.code()) {
1089 mov(rd, target, LeaveCC, cond);
1094 ldr(rd, MemOperand(FLAG_enable_ool_constant_pool ? pp : pc, 0), cond);
1101 Register rd,
1113 // However, if the original instruction is a 'mov rd, x' (not setting the
1114 // condition code), then replace it with a 'ldr rd, [pc]'.
1118 move_32_bit_immediate(rd, x, cond);
1121 addrmod1(instr, rn, rd, Operand(ip));
1131 ASSERT(!rn.is(pc) && !rd.is(pc) && !x.rm_.is(pc) && !x.rs_.is(pc));
1134 emit(instr | rn.code()*B16 | rd.code()*B12);
1142 void Assembler::addrmod2(Instr instr, Register rd, const MemOperand& x) {
1154 // rn (and rd in a load) should never be ip, or will be trashed.
1155 ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));
1157 addrmod2(instr, rd, MemOperand(x.rn_, ip, x.am_));
1170 emit(instr | am | x.rn_.code()*B16 | rd.code()*B12);
1174 void Assembler::addrmod3(Instr instr, Register rd, const MemOperand& x) {
1187 // rn (and rd in a load) should never be ip, or will be trashed.
1188 ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));
1190 addrmod3(instr, rd, MemOperand(x.rn_, ip, x.am_));
1197 // rn (and rd in a load) should never be ip, or will be trashed.
1198 ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));
1201 addrmod3(instr, rd, MemOperand(x.rn_, ip, x.am_));
1209 emit(instr | am | x.rn_.code()*B16 | rd.code()*B12);
1676 // Rd(15-12) | imm5(11-7) | 0(6) | 01(5-4) | Rm(3-0)
1695 // Rd(15-12) | imm5(11-7) | 1(6) | 01(5-4) | Rm(3-0)
1714 // Rd(15-12) | rotate(11-10) | 00(9-8)| 0111(7-4) | Rm(3-0)
1737 // Rd(15-12) | rotate(11-10) | 00(9-8)| 0111(7-4) | Rm(3-0)
1760 // Rd(15-12) | rotate(11-10) | 00(9-8)| 0111(7-4) | Rm(3-0)
1991 Register rd,
1998 rd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | B4 | crm.code());
2004 Register rd,
2008 mcr(coproc, opcode_1, rd, crn, crm, opcode_2, kSpecialCondition);
2014 Register rd,
2021 rd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | B4 | crm.code());
2027 Register rd,
2031 mrc(coproc, opcode_1, rd, crn, crm, opcode_2, kSpecialCondition);
3370 // Instruction to patch must be 'vldr rd, [pc, #offset]' with offset == 0.
3420 // ldr rd, [pc, #0]
3648 // Instruction to patch must be 'vldr rd, [pp, #0]'.
3655 // Instruction to patch must be 'ldr rd, [pp, #0]'.
