Lines Matching full:src3
317 void Push(Register src1, Register src2, Register src3, Condition cond = al) {
319 ASSERT(!src2.is(src3));
320 ASSERT(!src1.is(src3));
322 if (src2.code() > src3.code()) {
323 stm(db_w, sp, src1.bit() | src2.bit() | src3.bit(), cond);
326 str(src3, MemOperand(sp, 4, NegPreIndex), cond);
330 Push(src2, src3, cond);
337 Register src3,
341 ASSERT(!src2.is(src3));
342 ASSERT(!src1.is(src3));
345 ASSERT(!src3.is(src4));
347 if (src2.code() > src3.code()) {
348 if (src3.code() > src4.code()) {
351 src1.bit() | src2.bit() | src3.bit() | src4.bit(),
354 stm(db_w, sp, src1.bit() | src2.bit() | src3.bit(), cond);
359 Push(src3, src4, cond);
363 Push(src2, src3, src4, cond);
379 void Pop(Register src1, Register src2, Register src3, Condition cond = al) {
381 ASSERT(!src2.is(src3));
382 ASSERT(!src1.is(src3));
384 if (src2.code() > src3.code()) {
385 ldm(ia_w, sp, src1.bit() | src2.bit() | src3.bit(), cond);
387 ldr(src3, MemOperand(sp, 4, PostIndex), cond);
391 Pop(src2, src3, cond);
399 Register src3,
403 ASSERT(!src2.is(src3));
404 ASSERT(!src1.is(src3));
407 ASSERT(!src3.is(src4));
409 if (src2.code() > src3.code()) {
410 if (src3.code() > src4.code()) {
413 src1.bit() | src2.bit() | src3.bit() | src4.bit(),
417 ldm(ia_w, sp, src1.bit() | src2.bit() | src3.bit(), cond);
420 Pop(src3, src4, cond);
424 Pop(src2, src3, src4, cond);
