Lines Matching refs:rt
836 return i1->IsLdrLiteralX() && (i1->Rt() == ip0.code()) &&
892 LoadStoreOp Assembler::LoadOpFor(const CPURegister& rt) {
893 ASSERT(rt.IsValid());
894 if (rt.IsRegister()) {
895 return rt.Is64Bits() ? LDR_x : LDR_w;
897 ASSERT(rt.IsFPRegister());
898 return rt.Is64Bits() ? LDR_d : LDR_s;
903 LoadStorePairOp Assembler::LoadPairOpFor(const CPURegister& rt,
905 ASSERT(AreSameSizeAndType(rt, rt2));
907 if (rt.IsRegister()) {
908 return rt.Is64Bits() ? LDP_x : LDP_w;
910 ASSERT(rt.IsFPRegister());
911 return rt.Is64Bits() ? LDP_d : LDP_s;
916 LoadStoreOp Assembler::StoreOpFor(const CPURegister& rt) {
917 ASSERT(rt.IsValid());
918 if (rt.IsRegister()) {
919 return rt.Is64Bits() ? STR_x : STR_w;
921 ASSERT(rt.IsFPRegister());
922 return rt.Is64Bits() ? STR_d : STR_s;
927 LoadStorePairOp Assembler::StorePairOpFor(const CPURegister& rt,
929 ASSERT(AreSameSizeAndType(rt, rt2));
931 if (rt.IsRegister()) {
932 return rt.Is64Bits() ? STP_x : STP_w;
934 ASSERT(rt.IsFPRegister());
935 return rt.Is64Bits() ? STP_d : STP_s;
941 const CPURegister& rt, const CPURegister& rt2) {
942 ASSERT(AreSameSizeAndType(rt, rt2));
944 if (rt.IsRegister()) {
945 return rt.Is64Bits() ? LDNP_x : LDNP_w;
947 ASSERT(rt.IsFPRegister());
948 return rt.Is64Bits() ? LDNP_d : LDNP_s;
954 const CPURegister& rt, const CPURegister& rt2) {
955 ASSERT(AreSameSizeAndType(rt, rt2));
957 if (rt.IsRegister()) {
958 return rt.Is64Bits() ? STNP_x : STNP_w;
960 ASSERT(rt.IsFPRegister());
961 return rt.Is64Bits() ? STNP_d : STNP_s;
966 LoadLiteralOp Assembler::LoadLiteralOpFor(const CPURegister& rt) {
967 if (rt.IsRegister()) {
968 return rt.Is64Bits() ? LDR_x_lit : LDR_w_lit;
970 ASSERT(rt.IsFPRegister());
971 return rt.Is64Bits() ? LDR_d_lit : LDR_s_lit;
