Lines Matching refs:MO
215 hash_code llvm::hash_value(const MachineOperand &MO) {
216 switch (MO.getType()) {
219 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
221 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
223 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
225 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
227 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
229 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
232 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
233 MO.getOffset());
235 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
237 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
238 MO.getSymbolName());
240 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
241 MO.getOffset());
243 return hash_combine(MO.getType(), MO.getTargetFlags(),
244 MO.getBlockAddress(), MO.getOffset());
247 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
249 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
251 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
253 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
762 MachineMemOperand *MO) {
770 NewMemRefs[NewNum - 1] = MO;
813 const MachineOperand &MO = getOperand(i);
815 if (!MO.isReg()) {
816 if (!MO.isIdenticalTo(OMO))
824 if (MO.isDef()) {
828 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
830 if (MO.getReg() != OMO.getReg())
833 if (!MO.isIdenticalTo(OMO))
835 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
839 if (!MO.isIdenticalTo(OMO))
841 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
881 const MachineOperand &MO = getOperand(i);
882 if (!MO.isReg() || !MO.isImplicit())
1027 const MachineOperand &MO = getOperand(OpIdx);
1028 if (!MO.isReg() || MO.getReg() != Reg)
1038 const MachineOperand &MO = getOperand(OpIdx);
1039 assert(MO.isReg() &&
1042 if (unsigned SubIdx = MO.getSubReg()) {
1068 const MachineOperand &MO = getOperand(i);
1069 if (!MO.isReg() || !MO.isUse())
1071 unsigned MOReg = MO.getReg();
1079 if (!isKill || MO.isKill())
1096 const MachineOperand &MO = getOperand(i);
1097 if (!MO.isReg() || MO.getReg() != Reg)
1101 if (MO.isUse())
1102 Use |= !MO.isUndef();
1103 else if (MO.getSubReg() && !MO.isUndef())
1122 const MachineOperand &MO = getOperand(i);
1125 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1127 if (!MO.isReg() || !MO.isDef())
1129 unsigned MOReg = MO.getReg();
1138 if (Found && (!isDead || MO.isDead()))
1203 const MachineOperand &MO = getOperand(OpIdx);
1204 assert(MO.isTied() && "Operand isn't tied");
1207 if (MO.TiedTo < TiedMax)
1208 return MO.TiedTo - 1;
1213 if (MO.isUse())
1215 // MO is a def. Search for the tied use.
1261 MachineOperand &MO = getOperand(i);
1262 if (MO.isReg() && MO.isUse())
1263 MO.setIsKill(false);
1275 MachineOperand &MO = getOperand(i);
1276 if (!MO.isReg() || MO.getReg() != FromReg)
1278 MO.substPhysReg(ToReg, RegInfo);
1282 MachineOperand &MO = getOperand(i);
1283 if (!MO.isReg() || MO.getReg() != FromReg)
1285 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1426 const MachineOperand &MO = getOperand(i);
1427 if (!MO.isReg() || MO.isUse())
1429 if (!MO.isDead())
1441 const MachineOperand &MO = MI->getOperand(i);
1442 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1443 addOperand(MF, MO);
1532 const MachineOperand &MO = getOperand(i);
1534 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1535 VirtRegs.push_back(MO.getReg());
1539 // of registers. Don't rely on MO.isDead() because we may be called before
1542 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1543 unsigned Reg = MO.getReg();
1573 if (isDebugValue() && MO.isMetadata()) {
1575 const MDNode *MD = MO.getMetadata();
1579 MO.print(OS, TM);
1580 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1581 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1582 } else if (i == AsmDescOp && MO.isImm()) {
1585 unsigned Flag = MO.getImm();
1613 MO.print(OS, TM);
1693 MachineOperand &MO = getOperand(i);
1694 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1696 unsigned Reg = MO.getReg();
1702 if (MO.isKill())
1708 MO.setIsKill();
1711 } else if (hasAliases && MO.isKill() &&
1748 MachineOperand &MO = getOperand(i);
1749 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1751 unsigned OpReg = MO.getReg();
1753 MO.setIsKill(false);
1766 MachineOperand &MO = getOperand(i);
1767 if (!MO.isReg() || !MO.isDef())
1769 unsigned MOReg = MO.getReg();
1774 MO.setIsDead();
1776 } else if (hasAliases && MO.isDead() &&
1812 MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo);
1813 if (MO)
1817 const MachineOperand &MO = getOperand(i);
1818 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1819 MO.getSubReg() == 0)
1832 MachineOperand &MO = getOperand(i);
1833 if (MO.isRegMask()) {
1837 if (!MO.isReg() || !MO.isDef()) continue;
1838 unsigned Reg = MO.getReg();
1848 if (Dead) MO.setIsDead();
1866 const MachineOperand &MO = MI->getOperand(i);
1867 if (MO.isReg() && MO.isDef() &&
1868 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1871 HashComponents.push_back(hash_value(MO));
