Lines Matching refs:dag
76 // DAG subtrees must have at least this many nodes.
291 /// consistent with the DAG builder, which traverses the interior of the
294 /// This design avoids exposing scheduling boundaries to the DAG builder,
295 /// simplifying the DAG builder's support for "special" target instructions.
365 /// handle calls, the DAG builder needs to be modified to create register
403 // boundary at the bottom of the region. The DAG does not include RegionEnd,
644 // Build the DAG.
654 // Initialize the strategy before modifying the DAG.
662 // Initialize ready queues now that the DAG and priority data are finalized.
692 // Notify the scheduling strategy before updating the DAG.
740 /// Identify DAG roots and setup scheduler queues.
746 // Release all DAG roots for scheduling, not including EntrySU/ExitSU.
978 /// only includes instructions that have DAG nodes, not scheduling boundaries.
996 // Initialize the strategy before modifying the DAG.
1004 // Initialize ready queues now that the DAG and priority data are finalized.
1031 // Notify the scheduling strategy after updating the DAG.
1046 /// Build the DAG and setup three register pressure trackers.
1063 // Build the DAG, and compute current register pressure.
1080 /// Compute the max cyclic critical path through the DAG. The scheduling DAG
1215 // LoadClusterMutation - DAG post-processing to cluster loads.
1219 /// \brief Post-process the DAG to create cluster edges between neighboring
1241 void apply(ScheduleDAGMI *DAG) override;
1243 void clusterNeighboringLoads(ArrayRef<SUnit*> Loads, ScheduleDAGMI *DAG);
1248 ScheduleDAGMI *DAG) {
1270 && DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) {
1283 DAG->addEdge(SI->getSUnit(), SDep(SUb, SDep::Artificial));
1292 /// \brief Callback from DAG postProcessing to create cluster edges for loads.
1293 void LoadClusterMutation::apply(ScheduleDAGMI *DAG) {
1294 // Map DAG NodeNum to store chain ID.
1298 for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
1299 SUnit *SU = &DAG->SUnits[Idx];
1302 unsigned ChainPredID = DAG->SUnits.size();
1321 clusterNeighboringLoads(StoreChainDependents[Idx], DAG);
1325 // MacroFusion - DAG post-processing to encourage fusion of macro ops.
1329 /// \brief Post-process the DAG to create cluster edges between instructions
1336 void apply(ScheduleDAGMI *DAG) override;
1340 /// \brief Callback from DAG postProcessing to create cluster edges to encourage
1342 void MacroFusion::apply(ScheduleDAGMI *DAG) {
1344 MachineInstr *Branch = DAG
1348 for (unsigned Idx = DAG->SUnits.size(); Idx > 0;) {
1349 SUnit *SU = &DAG->SUnits[--Idx];
1359 bool Success = DAG->addEdge(&DAG->ExitSU, SDep(SU, SDep::Cluster));
1361 assert(Success && "No DAG nodes should be reachable from ExitSU");
1369 // CopyConstrain - DAG post-processing to encourage copy elimination.
1373 /// \brief Post-process the DAG to create weak edges from all uses of a copy to
1385 void apply(ScheduleDAGMI *DAG) override;
1388 void constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG);
1411 void CopyConstrain::constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG) {
1412 LiveIntervals *LIS = DAG->getLIS();
1480 SUnit *GlobalSU = DAG->getSUnit(GlobalDef);
1489 SUnit *LastLocalSU = DAG->getSUnit(LastLocalDef);
1497 if (!DAG->canAddEdge(GlobalSU, I->getSUnit()))
1506 SUnit *FirstLocalSU = DAG->getSUnit(FirstLocalDef);
1513 if (!DAG->canAddEdge(FirstLocalSU, I->getSUnit()))
1523 DAG->addEdge(GlobalSU, SDep(*I, SDep::Weak));
1529 DAG->addEdge(FirstLocalSU, SDep(*I, SDep::Weak));
1533 /// \brief Callback from DAG postProcessing to create weak edges to encourage
1535 void CopyConstrain::apply(ScheduleDAGMI *DAG) {
1536 assert(DAG->hasVRegLiveness() && "Expect VRegs with LiveIntervals");
1538 MachineBasicBlock::iterator FirstPos = nextIfDebug(DAG->begin(), DAG->end());
1539 if (FirstPos == DAG->end())
1541 RegionBeginIdx = DAG->getLIS()->getInstructionIndex(&*FirstPos);
1542 RegionEndIdx = DAG->getLIS()->getInstructionIndex(
1543 &*priorNonDebug(DAG->end(), DAG->begin()));
1545 for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
1546 SUnit *SU = &DAG->SUnits[Idx];
1550 constrainLocalCopy(SU, static_cast<ScheduleDAGMILive*>(DAG));
1564 // A new HazardRec is created for each DAG and owned by SchedBoundary.
1587 // latency of a DAG edge or the number of cycles that a processor resource is
1597 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) {
1603 I = DAG->SUnits.begin(), E = DAG->SUnits.end(); I != E; ++I) {
1604 const MCSchedClassDesc *SC = DAG->getSchedClass(&*I);
1618 init(ScheduleDAGMI *dag, const TargetSchedModel *smodel, SchedRemainder *rem) {
1620 DAG = dag;
1685 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
1888 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
2108 initResourceDelta(const ScheduleDAGMI *DAG,
2113 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
2342 void GenericScheduler::initialize(ScheduleDAGMI *dag) {
2343 assert(dag->hasVRegLiveness() &&
2345 DAG = static_cast<ScheduleDAGMILive*>(dag);
2346 SchedModel = DAG->getSchedModel();
2347 TRI = DAG->TRI;
2349 Rem.init(DAG, SchedModel);
2350 Top.init(DAG, SchedModel, &Rem);
2351 Bot.init(DAG, SchedModel, &Rem);
2358 const TargetMachine &TM = DAG->MF.getTarget();
2361 TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
2365 TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
2455 Rem.CriticalPath = DAG->ExitSU.getDepth();
2466 Rem.CyclicCritPath = DAG->computeCyclicCriticalPath();
2544 if (DAG->isTrackingPressure()) {
2550 DAG->getRegionCriticalPSets(),
2551 DAG->getRegPressure().MaxSetPressure);
2557 &DAG->getPressureDiff(TryCand.SU),
2559 DAG->getRegionCriticalPSets(),
2560 DAG->getRegPressure().MaxSetPressure);
2565 DAG->getPressureDiff(TryCand.SU),
2567 DAG->getRegionCriticalPSets(),
2568 DAG->getRegPressure().MaxSetPressure);
2590 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.Excess,
2596 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.CriticalMax,
2618 // the scheduler pass by combining the loads during DAG postprocessing.
2620 Zone.isTop() ? DAG->getNextClusterSucc() : DAG->getNextClusterPred();
2632 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.CurrentMax,
2638 TryCand.initResourceDelta(DAG, SchedModel);
2671 /// DAG building. To adjust for the current scheduling location we need to
2691 TryCand.initResourceDelta(DAG, SchedModel);
2723 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand);
2742 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand);
2759 if (DAG->top() == DAG->bottom()) {
2771 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand);
2783 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand);
2824 I->getSUnit()->dump(DAG));
2825 DAG->moveInstruction(Copy, InsertPos);
2854 ScheduleDAGMILive *DAG = new ScheduleDAGMILive(C, make_unique<GenericScheduler>(C));
2855 // Register DAG post-processors.
2860 DAG->addMutation(make_unique<CopyConstrain>(DAG->TII, DAG->TRI));
2861 if (EnableLoadCluster && DAG->TII->enableClusterLoads())
2862 DAG->addMutation(make_unique<LoadClusterMutation>(DAG->TII, DAG->TRI));
2864 DAG->addMutation(make_unique<MacroFusion>(DAG->TII));
2865 return DAG;
2876 void PostGenericScheduler::initialize(ScheduleDAGMI *Dag) {
2877 DAG = Dag;
2878 SchedModel = DAG->getSchedModel();
2879 TRI = DAG->TRI;
2881 Rem.init(DAG, SchedModel);
2882 Top.init(DAG, SchedModel, &Rem);
2888 const TargetMachine &TM = DAG->MF.getTarget();
2891 TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
2897 Rem.CriticalPath = DAG->ExitSU.getDepth();
2953 TryCand.initResourceDelta(DAG, SchedModel);
2964 if (DAG->top() == DAG->bottom()) {
2992 /// scheduled/remaining flags in the DAG nodes.
2998 /// Create a generic scheduler with no vreg liveness or DAG mutation passes.
3044 ScheduleDAGMILive *DAG;
3049 ILPScheduler(bool MaximizeILP): DAG(nullptr), Cmp(MaximizeILP) {}
3051 void initialize(ScheduleDAGMI *dag) override {
3052 assert(dag->hasVRegLiveness() && "ILPScheduler needs vreg liveness");
3053 DAG = static_cast<ScheduleDAGMILive*>(dag);
3054 DAG->computeDFSResult();
3055 Cmp.DFSResult = DAG->getDFSResult();
3056 Cmp.ScheduledTrees = &DAG->getScheduledTrees();
3076 << " ILP: " << DAG->getDFSResult()->getILP(SU)
3077 << " Tree: " << DAG->getDFSResult()->getSubtreeID(SU) << " @"
3078 << DAG->getDFSResult()->getSubtreeLevel(
3079 DAG->getDFSResult()->getSubtreeID(SU)) << '\n'
3251 const ScheduleDAGMI *DAG = static_cast<const ScheduleDAGMI*>(G);
3252 const SchedDFSResult *DFS = DAG->hasVRegLiveness() ?
3265 const ScheduleDAGMI *DAG = static_cast<const ScheduleDAGMI*>(G);
3266 const SchedDFSResult *DFS = DAG->hasVRegLiveness() ?
3279 /// viewGraph - Pop up a ghostview window with the reachable parts of the DAG
