Lines Matching refs:isSigned
102 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
104 unsigned NumOps, bool isSigned, SDLoc dl);
107 SDNode *Node, bool isSigned);
112 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
127 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
129 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
131 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
2032 bool isSigned) {
2039 Entry.isSExt = isSigned;
2040 Entry.isZExt = !isSigned;
2064 .setTailCall(isTailCall).setSExtResult(isSigned).setZExtResult(!isSigned);
2079 bool isSigned, SDLoc dl) {
2087 Entry.isSExt = isSigned;
2088 Entry.isZExt = !isSigned;
2099 .setSExtResult(isSigned).setZExtResult(!isSigned);
2111 bool isSigned) {
2121 Entry.isSExt = isSigned;
2122 Entry.isZExt = !isSigned;
2133 .setSExtResult(isSigned).setZExtResult(!isSigned);
2158 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2173 return ExpandLibCall(LC, Node, isSigned);
2177 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2182 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2183 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2184 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2185 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2186 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2194 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2196 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2198 if (isSigned)
2224 bool isSigned = Opcode == ISD::SDIVREM;
2229 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2230 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2231 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2232 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2233 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2250 Entry.isSExt = isSigned;
2251 Entry.isZExt = !isSigned;
2259 Entry.isSExt = isSigned;
2260 Entry.isZExt = !isSigned;
2270 .setSExtResult(isSigned).setZExtResult(!isSigned);
2398 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2419 if (isSigned) {
2440 SDValue Bias = DAG.getConstantFP(isSigned ?
2460 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2461 // Code below here assumes !isSigned without checking again.
2493 if (!isSigned) {
2599 bool isSigned,
2616 if (isSigned) continue;
2630 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2641 bool isSigned,
2661 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
3609 bool isSigned = Node->getOpcode() == ISD::SREM;
3610 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3611 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3615 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3618 useDivRem(Node, isSigned, false))) {
3626 } else if (isSigned)
3641 bool isSigned = Node->getOpcode() == ISD::SDIV;
3642 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3646 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3647 useDivRem(Node, isSigned, true)))
3650 else if (isSigned)
3796 bool isSigned = Node->getOpcode() == ISD::SMULO;
3797 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3799 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3800 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3801 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3805 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3806 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3841 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3852 if (isSigned) {
