Lines Matching defs:To
16 // to:
21 // Note that if a register allocator chooses to use this pass, that it
22 // has to be capable of handling the non-SSA nature of these rewritten
56 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
58 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
63 // Temporary flag to disable rescheduling.
91 // SrcRegMap - A map from virtual registers to physical registers which are
92 // likely targets to be coalesced to due to copies from physical registers to
96 // DstRegMap - A map from virtual registers to physical registers which are
97 // likely targets to be coalesced to due to copies to physical registers from
175 /// sink3AddrInstruction - A two-address instruction has been converted to a
176 /// three-address instruction to avoid clobbering a register. Try to sink it
177 /// past the instruction that would kill the above mentioned register to reduce
182 // FIXME: Shouldn't we be trying to do this before we three-addressify the
184 // the instruction to be in three-address form.
186 // Check if it's safe to move this instruction.
206 // Don't try to move it if it implicitly defines a register.
242 // appropriate location, we can try to sink the current instruction
249 // position and the kill use, then it's not safe to sink it.
251 // FIXME: This can be sped up if there is an easy way to query whether an
264 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
279 // Save the operand that kills the register. We want to unset the kill
300 // Move instruction to its destination.
370 // This is to match the kill flag version where undefs don't have kill
377 assert(I != LI.end() && "Reg must be live-in to use.");
386 /// coalescable copies to see if the original value is potentially not killed.
394 /// %reg1034 is not considered to be killed, since it is copied from a
408 // All uses of physical registers are likely to be kills.
424 // If the def is something other than a copy, then it isn't going to
477 /// might be mapped to.
503 /// isProfitableToCommute - Return true if it's potentially profitable to commute
512 // Determine if it's profitable to commute this two address instruction. In
521 // In this case, it might not be possible to coalesce the second MOV8rr
522 // instruction if the first one is coalesced. So it would be profitable to
542 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
585 DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
600 /// isProfitableToConv3Addr - Return true if it is profitable to convert the
601 /// given 2-address instruction to a 3-address one.
609 // Turn ADD into a 3-address instruction to avoid a copy.
632 DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
683 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!");
696 assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!");
701 assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");
707 /// source and destination registers might be mapped to. These are kept in
708 /// point-to maps used to determine future optimizations. e.g.
714 /// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
715 /// potentially joined with r1 on the output side. It's worthwhile to commute
716 /// 'add' to eliminate a copy.
732 "Can't map to two src physical registers!");
743 /// instruction in order to eliminate the need for the copy.
748 // Bail immediately if we don't have LV or LIS available. We use them to find
816 // Move the copies connected to MI down as well.
835 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
865 // Don't want to extend other live ranges and update kills.
884 // We have to move the copies first so that the MBB is still well-formed
913 /// instruction too close to the defs of its register dependencies.
934 /// current two-address instruction in order to eliminate the need for the
940 // Bail immediately if we don't have LV or LIS available. We use them to find
1014 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
1035 // Don't want to extend other live ranges and update kills.
1058 // Move the old kill above MI, don't forget to move debug info as well.
1063 MachineBasicBlock::iterator To = std::next(From);
1066 MBB->splice(InsertPos, MBB, From, To);
1086 /// coalescing away the register copy. Returns true if no copy needs to be
1087 /// inserted to untie mi's operands (either because they were untied, or
1109 // Check if it is profitable to commute the operands.
1135 // If it's profitable to commute, try to do so.
1154 // This instruction is potentially convertible to a true
1157 // Try to convert it.
1179 // because it's preferable to schedule a load than a register copy.
1210 // look "normal" to the transformation logic.
1278 // Transforming didn't eliminate the tie and didn't lead to an
1292 // Collect tied operands of MI that need to be handled.
1364 // The register is tied to multiple destinations (or else we would
1388 // If this operand is folding a truncation, the truncation now moves to the
1397 // The superreg class will not be used to constrain the subreg class.
1478 assert(I != LI.end() && "RegB must be live-in to use.");
1488 // removed from a different tied use of regB, so now we need to add
1489 // a kill flag to one of the remaining uses of regB.
1500 /// runOnMachineFunction - Reduce two-address instructions to two operands.
1574 // block to ease elimination. Continue processing with 'nmi'.
1586 DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1592 // To %reg:subidx = COPY %subreg
1600 DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
1650 // Nothing needs to be inserted for <undef> operands.
1654 // Defer any kill flag to the last operand using SrcReg. Otherwise, we
1676 // Return an iterator pointing to the first inserted instr.
