Lines Matching refs:Addr
115 bool ComputeAddress(const Value *Obj, Address &Addr);
116 bool SimplifyAddress(Address &Addr, MVT VT, int64_t ScaleFactor,
118 void AddLoadStoreOperands(Address &Addr, const MachineInstrBuilder &MIB,
125 bool EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
127 bool EmitStore(MVT VT, unsigned SrcReg, Address Addr,
306 bool AArch64FastISel::ComputeAddress(const Value *Obj, Address &Addr) {
333 return ComputeAddress(U->getOperand(0), Addr);
338 return ComputeAddress(U->getOperand(0), Addr);
344 return ComputeAddress(U->getOperand(0), Addr);
348 Address SavedAddr = Addr;
349 uint64_t TmpOffset = Addr.getOffset();
385 Addr.setOffset(TmpOffset);
386 if (ComputeAddress(U->getOperand(0), Addr))
390 Addr = SavedAddr;
400 Addr.setKind(Address::FrameIndexBase);
401 Addr.setFI(SI->second);
409 if (!Addr.isValid())
410 Addr.setReg(getRegForValue(Obj));
411 return Addr.isValid();
443 bool AArch64FastISel::SimplifyAddress(Address &Addr, MVT VT,
446 int64_t Offset = Addr.getOffset();
469 if (needsLowering && Addr.getKind() == Address::FrameIndexBase) {
473 .addFrameIndex(Addr.getFI())
476 Addr
477 Addr.setReg(ResultReg);
483 uint64_t UnscaledOffset = Addr.getOffset() * ScaleFactor;
484 unsigned ResultReg = FastEmit_ri_(MVT::i64, ISD::ADD, Addr.getReg(), false,
488 Addr.setReg(ResultReg);
489 Addr.setOffset(0);
494 void AArch64FastISel::AddLoadStoreOperands(Address &Addr,
497 int64_t Offset = Addr.getOffset();
499 if (Addr.getKind() == Address::FrameIndexBase) {
500 int FI = Addr.getFI();
510 MIB.addReg(Addr.getReg());
515 bool AArch64FastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
519 if (!UseUnscaled && Addr.getOffset() < 0)
565 int64_t Offset = Addr.getOffset();
568 return EmitLoad(VT, ResultReg, Addr, /*UseUnscaled*/ true);
570 Addr.setOffset(Offset / ScaleFactor);
574 if (!SimplifyAddress(Addr, VT, UseUnscaled ? 1 : ScaleFactor, UseUnscaled))
581 AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOLoad, UseUnscaled);
605 Address Addr;
606 if (!ComputeAddress(I->getOperand(0), Addr))
610 if (!EmitLoad(VT, ResultReg, Addr))
617 bool AArch64FastISel::EmitStore(MVT VT, unsigned SrcReg, Address Addr,
621 if (!UseUnscaled && Addr.getOffset() < 0)
660 int64_t Offset = Addr.getOffset();
663 return EmitStore(VT, SrcReg, Addr, /*UseUnscaled*/ true);
665 Addr.setOffset(Offset / ScaleFactor);
669 if (!SimplifyAddress(Addr, VT, UseUnscaled ? 1 : ScaleFactor, UseUnscaled))
685 AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOStore, UseUnscaled);
705 Address Addr;
706 if (!ComputeAddress(I->getOperand(1), Addr))
709 if (!EmitStore(VT, SrcReg, Addr))
1262 Address Addr;
1263 Addr.setKind(Address::RegBase);
1264 Addr.setReg(AArch64::SP);
1265 Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1267 if (!EmitStore(ArgVT, Arg, Addr))
