Lines Matching refs:getOpcode
211 return N->getOpcode() == Opc &&
290 switch (N.getOpcode()) {
343 if (N.getOpcode() == ISD::SIGN_EXTEND ||
344 N.getOpcode() == ISD::SIGN_EXTEND_INREG) {
346 if (N.getOpcode() == ISD::SIGN_EXTEND_INREG)
360 } else if (N.getOpcode() == ISD::ZERO_EXTEND ||
361 N.getOpcode() == ISD::ANY_EXTEND) {
372 } else if (N.getOpcode() == ISD::AND) {
395 if (DL->getOpcode() != AArch64ISD::DUPLANE16 &&
396 DL->getOpcode() != AArch64ISD::DUPLANE32)
400 if (SV.getOpcode() != ISD::INSERT_SUBVECTOR)
404 if (EV.getOpcode() != ISD::EXTRACT_SUBVECTOR)
439 if (Op1.getOpcode() != ISD::MUL ||
443 if (Op1.getOpcode() != ISD::MUL ||
540 if (N.getOpcode() == ISD::SHL) {
578 if (N.getOpcode() == ISD::FrameIndex) {
585 if (N.getOpcode() == AArch64ISD::ADDlow) {
610 if (Base.getOpcode() == ISD::FrameIndex) {
652 if (Base.getOpcode() == ISD::FrameIndex) {
679 assert(N.getOpcode() == ISD::SHL && "Invalid opcode.");
713 if (N.getOpcode() != ISD::ADD)
736 if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL &&
744 if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL &&
784 if (N.getOpcode() != ISD::ADD)
807 if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL &&
815 if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL &&
1303 assert(N->getOpcode() == ISD::AND &&
1339 if (VT == MVT::i64 && Op0->getOpcode() == ISD::ANY_EXTEND &&
1346 } else if (VT == MVT::i32 && Op0->getOpcode() == ISD::TRUNCATE &&
1400 if (N->getOpcode() != ISD::SRL)
1431 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) &&
1451 } else if (VT == MVT::i32 && N->getOpcode() == ISD::SRL &&
1452 N->getOperand(0).getNode()->getOpcode() == ISD::TRUNCATE) {
1485 Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMWri : AArch64::UBFMWri;
1487 Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMXri : AArch64::UBFMXri;
1498 switch (N->getOpcode()) {
1834 assert(N->getOpcode() == ISD::OR && "Expect a OR operation");
1926 if (N->getOpcode() != ISD::OR)
1960 switch (N->getOpcode()) {
2006 if (LN->getOperand(1).getOpcode() != AArch64ISD::ADDlow ||
2059 switch (Node->getOpcode()) {
