Lines Matching defs:shift
39 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
59 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
63 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
1132 // check we have to arithmetic shift right the 32nd bit of the result by
1140 // shift will not be folded into the compare (SUBS).
1167 // shift will not be folded into the compare (SUBS).
3692 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3695 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3738 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3741 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3980 // i.e. 0 to 4095 with optional shift by 12
3984 // left shift by 12.
5021 // Also, logical shift right -> sri, with the same structure.
5036 SDValue Shift = N->getOperand(1);
5037 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5038 // or AArch64ISD::VLSHR vector, #shift
5039 unsigned ShiftOpc = Shift.getOpcode();
5044 // Is the shift amount constant?
5045 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5054 // Is C1 == ~C2, taking into account how much one can shift elements of a
5065 SDValue Y = Shift.getOperand(0);
5071 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1));
5727 /// operand of a vector shift operation, where all the elements of the
5746 /// operand of a vector shift left operation. That value must be in the range:
5747 /// 0 <= Value < ElementBits for a left shift; or
5748 /// 0 <= Value <= ElementBits for a long left shift.
5750 assert(VT.isVector() && "vector shift count is not a vector type");
5758 /// operand of a vector shift right operation. For a shift opcode, the value
5761 /// 1 <= |Value| <= ElementBits for a right shift; or
5762 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
5765 assert(VT.isVector() && "vector shift count is not a vector type");
5786 llvm_unreachable("unexpected shift opcode");
5797 // Right shift immediate
5806 // Right shift register. Note, there is not a shift right register
5807 // instruction, but the shift left register instruction takes a signed
5808 // value, where negative numbers specify a right shift.
5811 // negate the shift amount
6221 unsigned shift = Log2_64(NumBytes);
6224 (Offset >> shift) << shift == Offset)
6285 // it with shift to let it be lowered to UBFX.
6315 unsigned Shift = (63 - LZ) / 16;
6317 return (Shift < 3) ? true : false;
6365 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
6718 SDValue Shift = N->getOperand(2);
6738 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
7042 llvm_unreachable("Unknown shift intrinsic");
