Lines Matching full:getdesc
45 const MCInstrDesc &Desc = MI->getDesc();
933 assert(MI->getDesc().getNumOperands() == 3 &&
962 assert(MI->getDesc().getNumOperands() == 4 &&
968 assert(MI->getDesc().getNumOperands() == 4 &&
990 assert(MI->getDesc().getNumOperands() == 3 && MI->getOperand(0).isReg() &&
1149 unsigned Width = getRegClass(LdSt->getDesc(), 0, TRI, MF)->getSize();