Lines Matching defs:Reg
112 // the range 0 to (reg.size -1).
652 unsigned Reg = MI->getOperand(OpNum++).getReg();
653 if (Reg != AArch64::XZR)
654 O << ", " << getRegisterName(Reg);
881 unsigned Reg = MI->getOperand(4).getReg();
885 O << ", " << getRegisterName(Reg);
895 unsigned Reg = Op.getReg();
896 O << getRegisterName(Reg);
915 unsigned Reg = Op.getReg();
916 if (Reg == AArch64::XZR)
919 O << getRegisterName(Reg);
928 unsigned Reg = Op.getReg();
929 O << getRegisterName(Reg, AArch64::vreg);
1108 static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {
1110 switch (Reg) {
1113 case AArch64::Q0: Reg = AArch64::Q1; break;
1114 case AArch64::Q1: Reg = AArch64::Q2; break;
1115 case AArch64::Q2: Reg = AArch64::Q3; break;
1116 case AArch64::Q3: Reg = AArch64::Q4; break;
1117 case AArch64::Q4: Reg = AArch64::Q5; break;
1118 case AArch64::Q5: Reg = AArch64::Q6; break;
1119 case AArch64::Q6: Reg = AArch64::Q7; break;
1120 case AArch64::Q7: Reg = AArch64::Q8; break;
1121 case AArch64::Q8: Reg = AArch64::Q9; break;
1122 case AArch64::Q9: Reg = AArch64::Q10; break;
1123 case AArch64::Q10: Reg = AArch64::Q11; break;
1124 case AArch64::Q11: Reg = AArch64::Q12; break;
1125 case AArch64::Q12: Reg = AArch64::Q13; break;
1126 case AArch64::Q13: Reg = AArch64::Q14; break;
1127 case AArch64::Q14: Reg = AArch64::Q15; break;
1128 case AArch64::Q15: Reg = AArch64::Q16; break;
1129 case AArch64::Q16: Reg = AArch64::Q17; break;
1130 case AArch64::Q17: Reg = AArch64::Q18; break;
1131 case AArch64::Q18: Reg = AArch64::Q19; break;
1132 case AArch64::Q19: Reg = AArch64::Q20; break;
1133 case AArch64::Q20: Reg = AArch64::Q21; break;
1134 case AArch64::Q21: Reg = AArch64::Q22; break;
1135 case AArch64::Q22: Reg = AArch64::Q23; break;
1136 case AArch64::Q23: Reg = AArch64::Q24; break;
1137 case AArch64::Q24: Reg = AArch64::Q25; break;
1138 case AArch64::Q25: Reg = AArch64::Q26; break;
1139 case AArch64::Q26: Reg = AArch64::Q27; break;
1140 case AArch64::Q27: Reg = AArch64::Q28; break;
1141 case AArch64::Q28: Reg = AArch64::Q29; break;
1142 case AArch64::Q29: Reg = AArch64::Q30; break;
1143 case AArch64::Q30: Reg = AArch64::Q31; break;
1146 Reg = AArch64::Q0;
1150 return Reg;
1156 unsigned Reg = MI->getOperand(OpNum).getReg();
1163 if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) ||
1164 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg))
1166 else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) ||
1167 MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg))
1169 else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) ||
1170 MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg))
1174 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0))
1175 Reg = FirstReg;
1176 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0))
1177 Reg = FirstReg;
1179 // If it's a D-regreg before
1181 if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) {
1184 Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC);
1187 for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
1188 O << getRegisterName(Reg, AArch64::vreg) << LayoutSuffix;
