Lines Matching refs:MF
60 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
65 if (!MF) return RegList;
67 const Function *F = MF->getFunction();
123 getReservedRegs(const MachineFunction &MF) const {
124 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
132 if (TFI->hasFP(MF))
134 if (hasBasePointer(MF))
175 ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
189 MachineFunction &MF) const {
190 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
196 return TFI->hasFP(MF) ? 4 : 5;
198 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
220 const MachineFunction &MF,
222 const MachineRegisterInfo &MRI = MF.getRegInfo();
234 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
268 MachineFunction &MF) const {
269 MachineRegisterInfo *MRI = &MF.getRegInfo();
309 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
310 const MachineFrameInfo *MFI = MF.getFrameInfo();
311 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
312 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
317 if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
340 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
341 const MachineRegisterInfo *MRI = &MF.getRegInfo();
342 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
347 if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
357 if (MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF))
365 needsStackRealignment(const MachineFunction &MF) const {
366 const MachineFrameInfo *MFI = MF.getFrameInfo();
367 const Function *F = MF.getFunction();
368 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
374 return requiresRealignment && canRealignStack(MF);
378 cannotEliminateFrame(const MachineFunction &MF) const {
379 const MachineFrameInfo *MFI = MF.getFrameInfo();
380 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack())
383 || needsStackRealignment(MF);
387 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
388 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
390 if (TFI->hasFP(MF))
404 MachineFunction &MF = *MBB.getParent();
405 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
406 MachineConstantPool *ConstantPool = MF.getConstantPool();
408 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
424 requiresRegisterScavenging(const MachineFunction &MF) const {
429 trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
434 requiresFrameIndexScavenging(const MachineFunction &MF) const {
439 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
531 MachineFunction &MF = *MI->getParent()->getParent();
532 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
533 MachineFrameInfo *MFI = MF.getFrameInfo();
534 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
560 if (TFI->hasFP(MF) &&
561 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
592 const MachineFunction &MF = *MBB->getParent();
594 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
596 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
608 MachineFunction &MF = *MBB.getParent();
610 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
611 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
707 MachineFunction &MF = *MBB.getParent();
709 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
711 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
712 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
718 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
726 assert(TFI->hasReservedCallFrame(MF) &&
729 assert(!MF.getFrameInfo()->hasVarSizedObjects() &&
765 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
