Lines Matching refs:Addr
173 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
176 bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
178 bool ARMComputeAddress(const Value *Obj, Address &Addr);
179 void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
218 void AddLoadStoreOperands(MVT VT, Address &Addr,
753 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
781 return ARMComputeAddress(U->getOperand(0), Addr);
785 return ARMComputeAddress(U->getOperand(0), Addr);
790 return ARMComputeAddress(U->getOperand(0), Addr);
793 Address SavedAddr = Addr;
794 int TmpOffset = Addr.Offset;
830 Addr.Offset = TmpOffset;
831 if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
834 Addr = SavedAddr;
844 Addr.BaseType = Address::FrameIndexBase;
845 Addr.Base.FI = SI->second;
853 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
854 return Addr.Base.Reg != 0;
857 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
867 needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
870 needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
871 Addr.Offset > -256);
874 needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
880 needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
887 if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
895 .addFrameIndex(Addr.Base.FI)
897 Addr.Base.Reg = ResultReg;
898 Addr.BaseType = Address::RegBase;
904 Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
905 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
906 Addr.Offset = 0;
910 void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
916 Addr.Offset /= 4;
919 if (Addr.BaseType == Address::FrameIndexBase) {
920 int FI = Addr.Base.FI;
921 int Offset = Addr.Offset;
934 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
938 MIB.addImm(Addr.Offset);
943 MIB.addReg(Addr.Base.Reg);
948 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
952 MIB.addImm(Addr.Offset);
958 bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
970 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
989 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1004 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1038 ARMSimplifyAddress(Addr, VT, useAM3);
1046 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1071 Address Addr;
1072 if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
1075 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
1081 bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
1101 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1114 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1128 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1162 ARMSimplifyAddress(Addr, VT, useAM3);
1169 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1191 Address Addr;
1192 if (!ARMComputeAddress(I->getOperand(1), Addr))
1195 if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
2004 Address Addr;
2005 Addr.BaseType = Address::RegBase;
2006 Addr.Base.Reg = ARM::SP;
2007 Addr.Offset = VA.getLocMemOffset();
2009 bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
2930 Address Addr;
2931 if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
2934 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
