Lines Matching refs:Ops
1498 SDValue Ops[]= { Base, AMOpc, getAL(CurDAG),
1501 MVT::i32, MVT::Other, Ops);
1505 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1508 MVT::i32, MVT::Other, Ops);
1554 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1557 MVT::Other, Ops);
1570 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1571 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1581 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1582 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1591 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1592 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1601 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1602 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1615 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1617 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1629 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1631 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1643 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1645 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1826 SmallVector<SDValue, 7> Ops;
1832 Ops.push_back(MemAddr);
1833 Ops.push_back(Align);
1844 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1846 Ops.push_back(Pred);
1847 Ops.push_back(Reg0);
1848 Ops.push_back(Chain);
1849 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1866 Ops.push_back(SDValue(VLdA, 1));
1867 Ops.push_back(Align);
1873 Ops.push_back(Reg0);
1875 Ops.push_back(SDValue(VLdA, 0));
1876 Ops.push_back(Pred);
1877 Ops.push_back(Reg0);
1878 Ops.push_back(Chain);
1879 VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, Ops);
1951 SmallVector<SDValue, 7> Ops;
1982 Ops.push_back(MemAddr);
1983 Ops.push_back(Align);
1993 Ops.push_back(Inc);
1995 Ops.push_back(Reg0);
1997 Ops.push_back(SrcReg);
1998 Ops.push_back(Pred);
1999 Ops.push_back(Reg0);
2000 Ops.push_back(Chain);
2001 SDNode *VSt = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2031 Ops.push_back(SDValue(VStA, 0));
2032 Ops.push_back(Align);
2038 Ops.push_back(Reg0);
2040 Ops.push_back(RegSeq);
2041 Ops.push_back(Pred);
2042 Ops.push_back(Reg0);
2043 Ops.push_back(Chain);
2045 Ops);
2116 SmallVector<SDValue, 8> Ops;
2117 Ops.push_back(MemAddr);
2118 Ops.push_back(Align);
2121 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
2142 Ops.push_back(SuperReg);
2143 Ops.push_back(getI32Imm(Lane));
2144 Ops.push_back(Pred);
2145 Ops.push_back(Reg0);
2146 Ops.push_back(Chain);
2150 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2213 SmallVector<SDValue, 6> Ops;
2214 Ops.push_back(MemAddr);
2215 Ops.push_back(Align);
2221 Ops.push_back(Inc);
2224 Ops.push_back(Reg0);
2226 Ops.push_back(Pred);
2227 Ops.push_back(Reg0);
2228 Ops.push_back(Chain);
2236 SDNode *VLdDup = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2275 SmallVector<SDValue, 6> Ops;
2277 Ops.push_back(N->getOperand(1));
2278 Ops.push_back(RegSeq);
2279 Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
2280 Ops.push_back(getAL(CurDAG)); // predicate
2281 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
2282 return CurDAG->getMachineNode(Opc, dl, VT, Ops);
2318 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2321 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2329 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc,
2331 return CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops);
2334 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2338 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2357 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2361 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2469 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2471 Ops);
2473 SDValue Ops[] = {
2481 Ops);
2496 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2498 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, Ops);
2502 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2505 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2531 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2532 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops);
2534 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2535 return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops);
2547 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2548 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops);
2550 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2551 return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops);
2590 SDValue Ops[] = { N0.getOperand(0), Imm16,
2592 return CurDAG->getMachineNode(Opc, dl, VT, Ops);
2605 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2607 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops);
2609 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2614 dl, MVT::i32, MVT::i32, Ops);
2621 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2623 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops);
2625 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2630 dl, MVT::i32, MVT::i32, Ops);
2635 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2638 return CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops);
2640 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2646 dl, MVT::i32, MVT::i32, Ops);
2651 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2654 return CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops);
2656 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2662 dl, MVT::i32, MVT::i32, Ops);
2703 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2705 MVT::Glue, Ops);
2732 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2733 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
2752 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2753 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
2771 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2772 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
3015 SmallVector<SDValue, 7> Ops;
3016 Ops.push_back(MemAddr);
3017 Ops.push_back(getAL(CurDAG));
3018 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3019 Ops.push_back(Chain);
3020 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
3069 SmallVector<SDValue, 7> Ops;
3071 Ops.push_back(Val0);
3072 Ops.push_back(Val1);
3075 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0));
3076 Ops.push_back(MemAddr);
3077 Ops.push_back(getAL(CurDAG));
3078 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3079 Ops.push_back(Chain);
3085 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
3265 SmallVector<SDValue, 6> Ops;
3267 Ops.push_back(N->getOperand(0));
3268 Ops.push_back(N->getOperand(1));
3269 Ops.push_back(getAL(CurDAG)); // Predicate
3270 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3271 return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops);
3282 SmallVector<SDValue, 6> Ops;
3283 Ops.push_back(RegSeq);
3284 Ops.push_back(N->getOperand(2));
3285 Ops.push_back(getAL(CurDAG)); // Predicate
3286 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3287 return CurDAG->getMachineNode(ARM::VTBL2, dl, VT, Ops);
3393 std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);
3394 Ops.push_back(T1.getValue(1));
3395 CurDAG->UpdateNodeOperands(GU, Ops);
