Lines Matching full:src3
1204 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
1207 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
1242 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1245 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
1278 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1281 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
1319 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1322 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1906 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1907 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1925 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1926 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1964 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1965 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1984 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1985 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
2202 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
2204 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
2238 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
2240 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
2272 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2274 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2312 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
2314 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
4267 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4269 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4275 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4277 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4283 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4286 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4344 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4346 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4352 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4354 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4360 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4362 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4801 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
4815 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
5523 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
5525 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5526 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
5528 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5530 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5531 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5532 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5533 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
