Lines Matching full:sched
341 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
354 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> {
366 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> {
377 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> {
398 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
410 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
426 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
437 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>;
442 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
455 Requires<[IsThumb]>, Sched<[WriteBrL]> {
469 Requires<[IsThumb, HasV5T]>, Sched<[WriteBrL]> {
484 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24;
494 Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>;
501 T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> {
513 Sched<[WriteBrTbl]>;
519 Sched<[WriteBrTbl]> {
530 T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> {
546 Requires<[IsThumb]>, Sched<[WriteBr]>;
556 Requires<[IsThumb, IsNotMachO]>, Sched<[WriteBr]>;
566 "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> {
576 "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> {
855 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
863 Sched<[WriteALU]> {
873 Sched<[WriteALU]>;
881 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
886 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
901 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
909 Sched<[WriteALU]> {
919 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
927 Sched<[WriteALU]>;
943 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>;
952 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> {
965 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>;
969 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> {
986 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
994 Sched<[WriteALU]> {
1004 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1012 Sched<[WriteALU]> {
1022 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1029 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> {
1047 T1Special<{1,0,?,?}>, Sched<[WriteALU]> {
1057 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> {
1088 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>;
1096 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1104 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1111 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1118 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1126 Sched<[WriteALU]>;
1133 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>;
1142 Sched<[WriteALU]>;
1150 Sched<[WriteALU]> {
1160 Sched<[WriteALU]>;
1168 Sched<[WriteALU]>;
1177 Sched<[WriteALU]>;
1186 Sched<[WriteALU]>;
1194 Sched<[WriteALU]>;
1212 Sched<[WriteALU]>;
1220 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1235 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> {
1245 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1250 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1262 Sched<[WriteBr]>;
1453 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;
1459 (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
