Lines Matching refs:RegNum
444 unsigned RegNum;
449 unsigned RegNum;
478 unsigned RegNum;
643 return Reg.RegNum;
1404 .contains(VectorList.RegNum));
1421 .contains(VectorList.RegNum));
1448 .contains(VectorList.RegNum));
1706 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1707 Inst.addOperand(MCOperand::CreateReg(RegNum));
2121 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2317 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2323 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2344 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2349 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2512 static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
2514 Op->Reg.RegNum = RegNum;
2529 static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
2532 Op->Reg.RegNum = RegNum;
2617 static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
2622 Op->VectorList.RegNum = RegNum;
2631 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
2634 Op->VectorList.RegNum = RegNum;
2643 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
2646 Op->VectorList.RegNum = RegNum;
2693 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
2696 Op->PostIdxReg.RegNum = RegNum;
2788 << PostIdxReg.RegNum;
2846 << VectorList.RegNum << ">";
2850 << VectorList.RegNum << ">";
2854 << VectorList.Count << " * " << VectorList.RegNum << ">";
2890 unsigned RegNum = MatchRegisterName(lowerCase);
2891 if (!RegNum) {
2892 RegNum = StringSwitch<unsigned>(lowerCase)
2915 if (!RegNum) {
2929 return RegNum;
