Lines Matching defs:Imm
86 unsigned &Reg, unsigned &Imm,
184 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
536 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
539 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups,
561 Imm = SImm;
1001 // {20-16} = imm{15-12}
1002 // {11-0} = imm{11-0}
1077 // {11-7} = imm
1111 unsigned Imm = MO1.getImm();
1112 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
1114 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
1117 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
1147 unsigned Imm = MO1.getImm();
1148 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1150 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1183 unsigned Imm = MO2.getImm();
1184 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1186 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1198 // [SP, #imm]
1214 // [Rn, #imm]
1279 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1327 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1333 // {11-7} = imm
1378 // Encoded as [Rn, Rm, imm].
1449 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1455 // {11-7} = imm
1544 const MCOperand &Imm = MI.getOperand(Op + 1);
1549 switch (Imm.getImm()) {
1568 const MCOperand &Imm = MI.getOperand(Op + 1);
1573 switch (Imm.getImm()) {
1595 const MCOperand &Imm = MI.getOperand(Op + 1);
1600 switch (Imm.getImm()) {
