Lines Matching refs:Hexagon
9 // The Hexagon processor has no instructions that load or store predicate
20 #include "Hexagon.h"
64 return "Hexagon Expand Predicate Spill Code";
86 if (Opc == Hexagon::STriw_pred) {
94 assert(Hexagon::PredRegsRegClass.contains(SrcReg) &&
96 if (!TII->isValidOffset(Hexagon::STriw_indexed, Offset)) {
97 if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) {
99 TII->get(Hexagon::CONST32_Int_Real),
101 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr),
104 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
107 TII->get(Hexagon::STriw_indexed))
111 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri),
113 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
116 TII->get(Hexagon::STriw_indexed))
122 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
125 TII->get(Hexagon::STriw_indexed)).
130 } else if (Opc == Hexagon::LDriw_pred) {
133 assert(Hexagon::PredRegsRegClass.contains(DstReg) &&
140 if (!TII->isValidOffset(Hexagon::LDriw, Offset)) {
141 if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) {
143 TII->get(Hexagon::CONST32_Int_Real),
145 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr),
149 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::LDriw),
153 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_PdRs),
156 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri),
158 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::LDriw),
162 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_PdRs),
166 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::LDriw),
168 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_PdRs),
187 const char *Name = "Hexagon Expand Predicate Spill Code";
188 PassInfo *PI = new PassInfo(Name, "hexagon-spill-pred",
