Lines Matching refs:Hexagon
10 // This pass identifies loops where we can generate the Hexagon hardware
30 #include "Hexagon.h"
83 const char *getPassName() const override { return "Hexagon Hardware Loops"; }
278 "Hexagon Hardware Loops", false, false)
282 "Hexagon Hardware Loops", false, false)
287 return MI->getOpcode() == Hexagon::LOOP0_r ||
288 MI->getOpcode() == Hexagon::LOOP0_i;
297 DEBUG(dbgs() << "********* Hexagon Hardware Loops *********\n");
357 bool isAdd = (UpdOpc == Hexagon::ADD_ri);
540 case Hexagon::CMPEQri:
541 case Hexagon::CMPEQrr:
544 case Hexagon::CMPGTUri:
545 case Hexagon::CMPGTUrr:
548 case Hexagon::CMPGTri:
549 case Hexagon::CMPGTrr:
553 case Hexagon::CMPbEQri_V4:
554 case Hexagon::CMPhEQri_V4: {
574 if (CondOpc == Hexagon::CMPbEQri_V4) {
577 } else { // Hexagon::CMPhEQri_V4
626 if (StartValInstr && StartValInstr->getOpcode() == Hexagon::TFRI)
631 if (EndValInstr && EndValInstr->getOpcode() == Hexagon::TFRI)
708 // will be "reg - imm". Hexagon's "subtract immediate" instruction
769 if (!SR && RC == &Hexagon::DoubleRegsRegClass)
771 const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass;
781 const MCInstrDesc &SubD = RegToReg ? TII->get(Hexagon::SUB_rr) :
782 (RegToImm ? TII->get(Hexagon::SUB_ri) :
783 TII->get(Hexagon::ADD_ri));
811 const MCInstrDesc &AddD = TII->get(Hexagon::ADD_ri);
832 const MCInstrDesc &LsrD = TII->get(Hexagon::LSR_ri);
863 if (R == Hexagon::LC0 || R == Hexagon::LC1 ||
864 R == Hexagon::SA0 || R == Hexagon::SA1)
1082 unsigned CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
1086 BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::LOOP0_r))
1095 if (!TII->isValidOffset(Hexagon::LOOP0_i, CountImm)) {
1096 unsigned CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
1097 BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::TFRI), CountReg)
1099 BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::LOOP0_r))
1102 BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::LOOP0_i))
1117 TII->get(Hexagon::ENDLOOP0)).addMBB(LoopStart);
1122 if (LastI->getOpcode() == Hexagon::JMP_t ||
1123 LastI->getOpcode() == Hexagon::JMP_f) {
1194 case Hexagon::TFRI:
1195 case Hexagon::TFRI64:
1196 case Hexagon::CONST32_Int_Real:
1197 case Hexagon::CONST64_Int_Real:
1277 bool isAdd = (UpdOpc == Hexagon::ADD_ri);
