Lines Matching refs:Hexagon
1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
10 // This file implements the interfaces that Hexagon uses to lower LLVM code
42 #define DEBUG_TYPE "hexagon-lowering"
45 EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden,
46 cl::desc("Control jump table emission on Hexagon target"));
63 // Implement calling convention for Hexagon.
188 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
189 Hexagon::R5
205 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
211 Hexagon::D1, Hexagon::D2
214 Hexagon::R1, Hexagon::R3
221 unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2);
262 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) {
277 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
678 // ShiftAmount = number of left-shifted bits in the Hexagon instruction.
799 // For Hexagon, the outgoing memory arguments area should be on top of the
853 // stack where the return value will be stored. For Hexagon, the location on
876 RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
881 RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
1053 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1054 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1057 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1058 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1061 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1119 // Hexagon V5 Support.
1306 // Hexagon has a i1 sign extending load.
1318 // Hexagon doesn't have sext_inreg, replace them with shl/sra.
1321 // Hexagon has no REM or DIVREM operations.
1350 // Hexagon has no select or setcc: expand to SELECT_CC.
1433 setExceptionPointerRegister(Hexagon::R20);
1434 setExceptionSelectorRegister(Hexagon::R21);
1436 setExceptionPointerRegister(Hexagon::R0);
1437 setExceptionSelectorRegister(Hexagon::R1);
1530 unsigned OffsetReg = Hexagon::R28;
1533 DAG.getRegister(Hexagon::R30, getPointerTy()),
1555 llvm_unreachable("TLS not implemented for Hexagon.");
1573 // Hexagon Scheduler Hooks
1580 case Hexagon::ADJDYNALLOC: {
1609 return std::make_pair(0U, &Hexagon::IntRegsRegClass);
1612 return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
