Lines Matching full:src3
99 (ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
101 ") $dst = ")#mnemonic#"($src2, $src3)",
176 (ins PredRegs:$src1, IntRegs:$src2, s8Ext: $src3),
178 ") $dst = ")#mnemonic#"($src2, #$src3)",
396 DoubleRegs:$src3),
397 "$dst = vmux($src1, $src2, $src3)",
402 IntRegs:$src2, IntRegs:$src3),
403 "$dst = mux($src1, $src2, $src3)",
406 (i32 IntRegs:$src3))))]>, ImmRegRel;
411 IntRegs:$src3),
412 "$dst = mux($src1, #$src2, $src3)",
415 (i32 IntRegs:$src3))))]>, ImmRegRel;
420 s8Ext:$src3),
421 "$dst = mux($src1, $src2, #$src3)",
424 s8ExtPred:$src3)))]>, ImmRegRel;
428 s8Imm:$src3),
429 "$dst = mux($src1, #$src2, #$src3)",
432 s8ImmPred:$src3)))]>;
712 PredRegs:$src3),
713 "$dst = valignb($src1, $src2, $src3)",
718 PredRegs:$src3),
719 "$dst = vspliceb($src1, $src2, $src3)",
984 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3),
986 ") ")#"$dst = "#mnemonic#"($src2+#$src3)",
1219 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1220 "$dst += mpyi($src2, #$src3)",
1222 (add (mul (i32 IntRegs:$src2), u8ExtPred:$src3),
1229 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1230 "$dst += mpyi($src2, $src3)",
1232 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1239 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1240 "$dst -= mpyi($src2, #$src3)",
1243 u8ExtPred:$src3)))],
1281 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1282 "$dst += mpy($src2, $src3)",
1285 (i64 (sext (i32 IntRegs:$src3)))),
1291 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1292 "$dst -= mpy($src2, $src3)",
1296 (i64 (sext (i32 IntRegs:$src3))))))],
1302 IntRegs:$src2, IntRegs:$src3),
1303 "$dst += mpyu($src2, $src3)",
1306 (i64 (anyext (i32 IntRegs:$src3)))),
1311 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1312 "$dst -= mpyu($src2, $src3)",
1316 (i64 (anyext (i32 IntRegs:$src3))))))],
1322 IntRegs:$src2, IntRegs:$src3),
1323 "$dst += add($src2, $src3)",
1325 (i32 IntRegs:$src3)),
1332 IntRegs:$src2, s8Ext:$src3),
1333 "$dst += add($src2, #$src3)",
1335 s8_16ExtPred:$src3),
1341 IntRegs:$src2, IntRegs:$src3),
1342 "$dst -= add($src2, $src3)",
1345 (i32 IntRegs:$src3))))],
1351 IntRegs:$src2, s8Ext:$src3),
1352 "$dst -= add($src2, #$src3)",
1355 s8_16ExtPred:$src3)))],
1397 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
1399 ") ")#mnemonic#"($src2++#$offset) = $src3",
1533 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
1535 ") ")#mnemonic#"($src2+#$src3) = $src4",
1559 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1560 mnemonic#"($src1+#$src2) = $src3",
1744 u3Imm:$src3),
1745 "$dst = addasl($src1, $src2, #$src3)",
1748 u3ImmPred:$src3)))]>;
1844 IntRegs:$src3),
1849 (i32 IntRegs:$src3))))]>;
1852 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
1856 s12ImmPred:$src3)))]>;
1860 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
1864 (i32 IntRegs:$src3))))]>;
1868 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
1872 s12ImmPred:$src3)))]>;
2173 (i32 IntRegs:$src3),
2176 (i32 IntRegs:$src4), (i32 IntRegs:$src3)))>,
2180 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
2181 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
2187 (i32 IntRegs:$src3)),
2188 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
2193 def : Pat <(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s12ImmPred:$src3),
2194 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
2277 (i64 DoubleRegs:$src3)),
2281 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2286 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2292 (i1 PredRegs:$src3)),
2294 (AND_pp (NOT_p (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
2752 (ins IntRegs:$src1, IntRegs:$src2, u5Imm:$src3),
2753 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
2757 u5ImmPred:$src3)))],
2761 (ins DoubleRegs:$src1, DoubleRegs:$src2, u6Imm:$src3),
2762 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
2764 (OpNode1 (i64 DoubleRegs:$src2), u6ImmPred:$src3)))],
2772 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2773 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
2777 (i32 IntRegs:$src3))))],
2781 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2782 src3)")),
2786 (i32 IntRegs:$src3))))],
