Lines Matching full:src3
238 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset),
240 ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$offset)",
492 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
495 ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5",
513 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
514 mnemonic#"($src1+$src2<<#$src3) = $src4",
531 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
534 ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5.new",
552 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
553 mnemonic#"($src1+$src2<<#$src3) = $src4.new",
585 u2ImmPred:$src3))),
587 u2ImmPred:$src3, IntRegs:$src4)>;
591 u2ImmPred:$src3))),
593 u2ImmPred:$src3, IntRegs:$src4)>;
596 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
598 u2ImmPred:$src3, IntRegs:$src4)>;
601 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
603 u2ImmPred:$src3, DoubleRegs:$src4)>;
609 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, RC:$src4),
610 mnemonic#"($src1<<#$src2+##$src3) = $src4",
613 u0AlwaysExtPred:$src3))]>,
619 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
620 mnemonic#"($src1<<#$src2+##$src3) = $src4.new",
645 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
646 (I IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
650 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
651 (I IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
680 (ins PredRegs:$src1, IntRegs:$src2, OffsetOp:$src3, s6Ext:$src4),
682 ") ")#mnemonic#"($src2+#$src3) = #$src4",
700 (ins IntRegs:$src1, OffsetOp:$src2, s8Ext:$src3),
701 mnemonic#"($src1+#$src2) = #$src3",
725 def: Pat<(truncstorei8 s8ExtPred:$src3, (add IntRegs:$src1, u6_0ImmPred:$src2)),
726 (STrib_imm_V4 IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>;
728 def: Pat<(truncstorei16 s8ExtPred:$src3, (add IntRegs:$src1,
730 (STrih_imm_V4 IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>;
732 def: Pat<(store s8ExtPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2)),
733 (STriw_imm_V4 IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>;
818 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
820 ") ")#mnemonic#"($src2+#$src3) = $src4.new",
843 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
844 mnemonic#"($src1+#$src2) = $src3.new",
934 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
936 ") ")#mnemonic#"($src2++#$offset) = $src3.new",
1200 (ins IntRegs:$src1, IntRegs:$src2, s6Ext:$src3),
1201 "$dst = add($src1, add($src2, #$src3))",
1204 s6_16ExtPred:$src3)))]>,
1211 (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
1212 "$dst = add($src1, sub(#$src2, $src3))",
1215 (i32 IntRegs:$src3))))]>,
1224 (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
1225 "$dst = add($src1, sub(#$src2, $src3))",
1228 (i32 IntRegs:$src3)))]>,
1263 (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
1264 "$dst ^= xor($src2, $src3)",
1267 (i64 DoubleRegs:$src3))))],
1277 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1278 "$dst = or($src1, and($src2, #$src3))",
1281 s10ExtPred:$src3)))],
1289 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1290 src3)",
1293 (i32 IntRegs:$src3))))],
1300 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1301 "$dst |= and($src2, $src3)",
1304 (i32 IntRegs:$src3))))],
1311 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1312 "$dst ^= and($src2, $src3)",
1315 (i32 IntRegs:$src3))))],
1323 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1324 "$dst &= and($src2, ~$src3)",
1327 (not (i32 IntRegs:$src3)))))],
1334 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1335 "$dst |= and($src2, ~$src3)",
1338 (not (i32 IntRegs:$src3)))))],
1345 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1346 "$dst ^= and($src2, ~$src3)",
1349 (not (i32 IntRegs:$src3)))))],
1357 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1358 "$dst &= or($src2, $src3)",
1361 (i32 IntRegs:$src3))))],
1368 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1369 "$dst |= or($src2, $src3)",
1372 (i32 IntRegs:$src3))))],
1379 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1380 "$dst ^= or($src2, $src3)",
1383 (i32 IntRegs:$src3))))],
1391 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1392 "$dst &= xor($src2, $src3)",
1395 (i32 IntRegs:$src3))))],
1402 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1403 "$dst |= xor($src2, $src3)",
1406 (i32 IntRegs:$src3))))],
1413 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1414 "$dst ^= xor($src2, $src3)",
1417 (i32 IntRegs:$src3))))],
1425 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1426 "$dst |= and($src2, #$src3)",
1429 s10ExtPred:$src3)))],
1437 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1438 "$dst |= or($src2, #$src3)",
1441 s10ExtPred:$src3)))],
1493 (ins u6Ext:$src1, IntRegs:$src2, u6Imm:$src3),
1494 "$dst = add(#$src1, mpyi($src2, #$src3))",
1496 (add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
1501 def : Pat <(add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
1504 u6ImmPred:$src3))>;
1510 (ins u6Ext:$src1, IntRegs:$src2, IntRegs:$src3),
1511 "$dst = add(#$src1, mpyi($src2, $src3))",
1513 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1518 def : Pat <(add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1521 IntRegs:$src3))>;
1526 (ins IntRegs:$src1, u6Imm:$src2, IntRegs:$src3),
1527 "$dst = add($src1, mpyi(#$src2, $src3))",
1529 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3),
1537 (ins IntRegs:$src1, IntRegs:$src2, u6Ext:$src3),
1538 "$dst = add($src1, mpyi($src2, #$src3))",
1541 u6ExtPred:$src3)))]>,
1547 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1548 "$dst = add($src1, mpyi($src2, $src3))",
1551 (i32 IntRegs:$src3))))],
1599 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1600 "$dst = add(#$src1, asl($src2, #$src3))",
1602 (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1611 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1612 "$dst = add(#$src1, lsr($src2, #$src3))",
1614 (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1623 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1624 "$dst = sub(#$src1, asl($src2, #$src3))",
1626 (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1635 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1636 "$dst = sub(#$src1, lsr($src2, #$src3))",
1638 (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1649 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1650 "$dst = and(#$src1, asl($src2, #$src3))",
1652 (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1661 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1662 "$dst = and(#$src1, lsr($src2, #$src3))",
1664 (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1673 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1674 "$dst = or(#$src1, asl($src2, #$src3))",
1676 (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1685 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1686 "$dst = or(#$src1, lsr($src2, #$src3))",
1688 (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1707 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1708 "$dst ^= asl($src2, $src3)",
1711 (i32 IntRegs:$src3))))],
1717 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1718 "$dst ^= asr($src2, $src3)",
1721 (i32 IntRegs:$src3))))],
1727 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1728 "$dst ^= lsl($src2, $src3)",
1731 (i32 IntRegs:$src3))))],
1737 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1738 "$dst ^= lsr($src2, $src3)",
1741 (i32 IntRegs:$src3))))],
3190 (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
3191 "memw($src1+#$src2) = ##$src3",
3192 [(store (HexagonCONST32 tglobaladdr:$src3),
3288 (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
3289 "memh($src1+#$src2) = ##$src3",
3290 [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
