Lines Matching refs:Hexagon
20 #include "Hexagon.h"
55 static cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles",
84 return "Hexagon Packetizer";
175 INITIALIZE_PASS_BEGIN(HexagonPacketizer, "packets", "Hexagon Packetizer",
181 INITIALIZE_PASS_END(HexagonPacketizer, "packets", "Hexagon Packetizer",
269 return ((MI->getOpcode() == Hexagon::CALLR) ||
270 (MI->getOpcode() == Hexagon::CALLRv3));
278 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
296 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
308 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
343 if (RC == &Hexagon::PredRegsRegClass) {
371 return (MI->getOpcode() == Hexagon::JMP);
376 case Hexagon::BARRIER:
387 return (MI->getOpcode() == Hexagon::LOOP0_i ||
388 MI->getOpcode() == Hexagon::LOOP0_r);
440 if (RC == &Hexagon::PredRegsRegClass)
568 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
569 PacketSU->getInstr()->getOpcode() == Hexagon::DEALLOCFRAME)
573 if (PacketRC == &Hexagon::DoubleRegsRegClass) {
615 if (predRegClass == &Hexagon::PredRegsRegClass) {
619 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
627 if (predRegClass == &Hexagon::PredRegsRegClass) {
631 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
764 if (RC == &Hexagon::PredRegsRegClass && isCondInst(MI))
766 else if (RC != &Hexagon::PredRegsRegClass &&
853 Hexagon::PredRegsRegClass.contains(Op.getReg()))
913 Hexagon::PredRegsRegClass.contains(
938 Hexagon::PredRegsRegClass.contains(PReg1) &&
939 Hexagon::PredRegsRegClass.contains(PReg2) &&
986 // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
1015 if (I->getOpcode() == Hexagon::INLINEASM)
1122 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
1286 && J->getOpcode() == Hexagon::ALLOCFRAME
1287 && (I->getOpcode() == Hexagon::STrid
1288 || I->getOpcode() == Hexagon::STriw
1289 || I->getOpcode() == Hexagon::STrib)
