Lines Matching refs:VT
88 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
89 unsigned StoreSize = VT.getStoreSizeInBits();
98 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
99 unsigned StoreSize = VT.getStoreSizeInBits();
246 for (MVT VT : ScalarIntVTs) {
247 setOperationAction(ISD::SREM, VT, Expand);
248 setOperationAction(ISD::SDIV, VT, Expand);
251 setOperationAction(ISD::SDIVREM, VT, Custom);
252 setOperationAction(ISD::UDIVREM, VT, Custom);
255 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
256 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
258 setOperationAction(ISD::BSWAP, VT, Expand);
259 setOperationAction(ISD::CTTZ, VT, Expand);
260 setOperationAction(ISD::CTLZ, VT, Expand);
287 for (MVT VT : VectorIntTypes) {
289 setOperationAction(ISD::ADD, VT, Expand);
290 setOperationAction(ISD::AND, VT, Expand);
291 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
292 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
293 setOperationAction(ISD::MUL, VT, Expand);
294 setOperationAction(ISD::OR, VT, Expand);
295 setOperationAction(ISD::SHL, VT, Expand);
296 setOperationAction(ISD::SRA, VT, Expand);
297 setOperationAction(ISD::SRL, VT, Expand);
298 setOperationAction(ISD::ROTL, VT, Expand);
299 setOperationAction(ISD::ROTR, VT, Expand);
300 setOperationAction(ISD::SUB, VT, Expand);
301 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
302 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
304 setOperationAction(ISD::SDIV, VT, Expand);
305 setOperationAction(ISD::UDIV, VT, Expand);
306 setOperationAction(ISD::SREM, VT, Expand);
307 setOperationAction(ISD::UREM, VT, Expand);
308 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
309 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
310 setOperationAction(ISD::SDIVREM, VT, Custom);
311 setOperationAction(ISD::UDIVREM, VT, Custom);
312 setOperationAction(ISD::ADDC, VT, Expand);
313 setOperationAction(ISD::SUBC, VT, Expand);
314 setOperationAction(ISD::ADDE, VT, Expand);
315 setOperationAction(ISD::SUBE, VT, Expand);
316 setOperationAction(ISD::SELECT, VT, Expand);
317 setOperationAction(ISD::VSELECT, VT, Expand);
318 setOperationAction(ISD::SELECT_CC, VT, Expand);
319 setOperationAction(ISD::XOR, VT, Expand);
320 setOperationAction(ISD::BSWAP, VT, Expand);
321 setOperationAction(ISD::CTPOP, VT, Expand);
322 setOperationAction(ISD::CTTZ, VT, Expand);
323 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
324 setOperationAction(ISD::CTLZ, VT, Expand);
325 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
326 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
333 for (MVT VT : FloatVectorTypes) {
334 setOperationAction(ISD::FABS, VT, Expand);
335 setOperationAction(ISD::FADD, VT, Expand);
336 setOperationAction(ISD::FCEIL, VT, Expand);
337 setOperationAction(ISD::FCOS, VT, Expand);
338 setOperationAction(ISD::FDIV, VT, Expand);
339 setOperationAction(ISD::FEXP2, VT, Expand);
340 setOperationAction(ISD::FLOG2, VT, Expand);
341 setOperationAction(ISD::FPOW, VT, Expand);
342 setOperationAction(ISD::FFLOOR, VT, Expand);
343 setOperationAction(ISD::FTRUNC, VT, Expand);
344 setOperationAction(ISD::FMUL, VT, Expand);
345 setOperationAction(ISD::FMA, VT, Expand);
346 setOperationAction(ISD::FRINT, VT, Expand);
347 setOperationAction(ISD::FNEARBYINT, VT, Expand);
348 setOperationAction(ISD::FSQRT, VT, Expand);
349 setOperationAction(ISD::FSIN, VT, Expand);
350 setOperationAction(ISD::FSUB, VT, Expand);
351 setOperationAction(ISD::FNEG, VT, Expand);
352 setOperationAction(ISD::SELECT, VT, Expand);
353 setOperationAction(ISD::VSELECT, VT, Expand);
354 setOperationAction(ISD::SELECT_CC, VT, Expand);
355 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
356 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
399 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
400 EVT ScalarVT = VT.getScalarType();
405 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
406 EVT ScalarVT = VT.getScalarType();
427 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
428 assert(VT.isFloatingPoint());
429 return VT == MVT::f32;
432 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
433 assert(VT.isFloatingPoint());
434 return VT == MVT::f32;
603 EVT VT = EVT::getEVT(InitTy);
605 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
611 EVT VT = EVT::getEVT(CFP->getType());
613 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
641 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
642 NumElements = VT->getNumElements();
660 EVT VT = EVT::getEVT(InitTy);
662 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
759 EVT VT = Op.getValueType();
761 VT.getVectorNumElements());
785 EVT VT = Op.getValueType();
796 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
800 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
807 return DAG.getUNDEF(VT);
815 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, VT,
820 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
824 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
828 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
832 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
835 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
838 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
841 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
844 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
847 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
850 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
853 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
857 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
861 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
865 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
869 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
873 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
876 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
879 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
882 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
885 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
891 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
897 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
903 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
908 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
911 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
914 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
916 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
924 EVT VT = Op.getValueType();
925 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
928 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
936 EVT VT = Op.getValueType();
937 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
940 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
942 return DAG.getNode(ISD::FADD, DL, VT,
943 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
951 EVT VT = N->getValueType(0);
959 if (VT != MVT::f32 ||
986 return DAG.getNode(Opc, DL, VT, LHS, RHS);
995 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1054 EVT VT = Value.getValueType();
1055 EVT ElemVT = VT.getVectorElementType();
1127 EVT VT = Op.getValueType();
1130 if (ExtType != ISD::NON_EXTLOAD && !VT.isVector() && VT.getSizeInBits() > 32) {
1141 DAG.getNode(ISD::getExtForLoadExtType(ExtType), DL, VT, ExtLoad32),
1148 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1149 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1161 DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),
1527 EVT VT = Op.getValueType();
1534 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1537 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
1540 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1543 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1547 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1552 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1555 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1558 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1561 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1565 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1568 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
1571 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1575 DAG.getConstant(-1, VT),
1576 DAG.getConstant(0, VT),
1581 DAG.getConstant(-1, VT),
1582 DAG.getConstant(0, VT),
1585 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1591 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1592 DAG.getConstant(1, VT));
1595 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1596 DAG.getConstant(1, VT));
1599 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1603 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1609 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1612 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1615 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1619 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1631 EVT VT = Op.getValueType();
1633 SDValue Zero = DAG.getConstant(0, VT);
1634 SDValue NegOne = DAG.getConstant(-1, VT);
1641 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1644 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1645 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1647 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1648 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1650 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1653 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1654 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1656 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1657 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1821 MVT VT = Op.getSimpleValueType();
1823 SDValue Shift = DAG.getConstant(BitsDiff, VT);
1825 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Op.getOperand(0), Shift);
1827 return DAG.getNode(ISD::SRA, DL, VT, Shl, Shift);
1833 MVT VT = Op.getSimpleValueType();
1834 MVT ScalarVT = VT.getScalarType();
1836 if (!VT.isVector())
1843 unsigned NElts = VT.getVectorNumElements();
1851 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
1860 EVT VT = Op.getValueType();
1863 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
1867 EVT VT = Op.getValueType();
1871 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
1873 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
1880 EVT VT = Op.getValueType();
1882 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
1902 EVT VT = N->getValueType(0);
1904 if (VT.isVector() || VT.getSizeInBits() > 32)
1928 return DAG.getSExtOrTrunc(Mul, DL, VT);
2045 if (Ins[i].ArgVT == Ins[i].VT) {
2050 EVT VT;
2051 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2053 VT = Ins[i].ArgVT.getVectorElementType();
2054 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2056 Ins[i].VT.getVectorElementType()) {
2058 VT = Ins[i].ArgVT;
2061 VT = Ins[i].VT;
2064 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2092 unsigned Reg, EVT VT) const {
2102 return DAG.getRegister(VirtualRegister, VT);
