Lines Matching refs:dag
27 void R600SchedStrategy::initialize(ScheduleDAGMI *dag) {
28 assert(dag->hasVRegLiveness() && "R600SchedStrategy needs vreg liveness");
29 DAG = static_cast<ScheduleDAGMILive*>(dag);
30 TII = static_cast<const R600InstrInfo*>(DAG->TII);
31 TRI = static_cast<const R600RegisterInfo*>(DAG->TRI);
32 VLIW5 = !DAG->MF.getTarget().getSubtarget<AMDGPUSubtarget>().hasCaymanISA();
33 MRI = &DAG->MRI;
40 const AMDGPUSubtarget &ST = DAG->TM.getSubtarget<AMDGPUSubtarget>();
128 SU->dump(DAG);
131 for (unsigned i = 0; i < DAG->SUnits.size(); i++) {
132 const SUnit &S = DAG->SUnits[i];
134 S.dump(DAG);
191 DEBUG(dbgs() << "Top Releasing ";SU->dump(DAG););
195 DEBUG(dbgs() << "Bottom Releasing ";SU->dump(DAG););
