Lines Matching refs:Kind
59 unsigned Kind) override;
148 } Kind;
159 RegisterKind Kind;
179 SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
181 bool isToken() const override { return Kind == k_Token; }
182 bool isReg() const override { return Kind == k_Register; }
183 bool isImm() const override { return Kind == k_Immediate; }
185 bool isMEMrr() const { return Kind == k_MemoryReg; }
186 bool isMEMri() const { return Kind == k_MemoryImm; }
189 return (Kind == k_Register && Reg.Kind == rk_FloatReg);
193 return (Kind == k_Register && (Reg.Kind == rk_FloatReg
194 || Reg.Kind == rk_DoubleReg));
199 assert(Kind == k_Token && "Invalid access!");
204 assert((Kind == k_Register) && "Invalid access!");
209 assert((Kind == k_Immediate) && "Invalid access!");
214 assert((Kind == k_MemoryReg || Kind == k_MemoryImm) && "Invalid access!");
219 assert((Kind == k_MemoryReg) && "Invalid access!");
224 assert((Kind == k_MemoryImm) && "Invalid access!");
238 switch (Kind) {
299 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind,
303 Op->Reg.Kind = (SparcOperand::RegisterKind)Kind;
320 assert(Op.Reg.Kind == rk_FloatReg);
325 Op.Reg.Kind = rk_DoubleReg;
332 switch (Op.Reg.Kind) {
333 default: llvm_unreachable("Unexpected register kind!");
348 Op.Reg.Kind = rk_QuadReg;
355 Op->Kind = k_MemoryReg;
376 Op->Kind = k_MemoryImm;
923 unsigned Kind) {
926 switch (Kind) {
