Lines Matching refs:IndexReg
253 unsigned BaseReg, IndexReg, TmpReg, Scale;
262 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
267 unsigned getIndexReg() { return IndexReg; }
355 // If we already have a BaseReg, then assume this is the IndexReg with
360 assert (!IndexReg && "BaseReg/IndexReg already set!");
361 IndexReg = TmpReg;
392 // If we already have a BaseReg, then assume this is the IndexReg with
397 assert (!IndexReg && "BaseReg/IndexReg already set!");
398 IndexReg = TmpReg;
434 assert (!IndexReg && "IndexReg already set!");
436 IndexReg = Reg;
483 assert (!IndexReg && "IndexReg already set!");
484 IndexReg = TmpReg;
570 // If we already have a BaseReg, then assume this is the IndexReg with
575 assert (!IndexReg && "BaseReg/IndexReg already set!");
576 IndexReg = TmpReg;
681 unsigned IndexReg, unsigned Scale, SMLoc Start,
772 static bool CheckBaseRegAndIndexReg(unsigned BaseReg, unsigned IndexReg,
776 // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
777 if (BaseReg != 0 && IndexReg != 0) {
779 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
780 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) &&
781 IndexReg != X86::RIZ) {
786 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
787 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) &&
788 IndexReg != X86::EIZ){
793 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
794 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {
799 IndexReg != X86::SI && IndexReg != X86::DI) ||
801 IndexReg != X86::BX && IndexReg != X86::BP)) {
945 /*IndexReg=*/0, /*Scale=*/1, Loc, Loc, 0);
953 /*IndexReg=*/0, /*Scale=*/1, Loc, Loc, 0);
979 unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,
1012 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1026 // bracketed expression (i.e., ImmDisp [ BaseReg + Scale*IndexReg + Disp])
1207 // Parse [ Symbol + ImmDisp ] and [ BaseReg + Scale*IndexReg + ImmDisp ]. We
1246 int IndexReg = SM.getIndexReg();
1250 if (!BaseReg && !IndexReg) {
1257 if (CheckBaseRegAndIndexReg(BaseReg, IndexReg, ErrMsg)) {
1261 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1266 return CreateMemForInlineAsm(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1326 return X86Operand::CreateMem(SegReg, Disp, /*BaseReg=*/0, /*IndexReg=*/0,
1349 return CreateMemForInlineAsm(/*SegReg=*/0, Val, /*BaseReg=*/0,/*IndexReg=*/0,
1360 // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1380 return CreateMemForInlineAsm(/*SegReg=*/0, Val, /*BaseReg=*/0, /*IndexReg=*/0,
1408 return X86Operand::CreateMem(/*SegReg=*/0, Disp, /*BaseReg=*/1, /*IndexReg=*/0,
1592 // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1713 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
1770 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
1796 if (ParseRegister(IndexReg, L, L)) return nullptr;
1864 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {
1870 if (CheckBaseRegAndIndexReg(BaseReg, IndexReg, ErrMsg)) {
1875 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
2010 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
2022 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
