Lines Matching defs:Reg
128 unsigned Reg = MO.getReg();
129 if (!Reg)
131 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
170 unsigned Reg = isSub
173 if (Reg) {
178 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
299 unsigned Reg = II->first;
301 if (Reg == X86::EAX || Reg == X86::AX ||
302 Reg == X86::AH || Reg == X86::AL)
327 unsigned Reg = I->getReg();
329 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
374 pushq %<reg>
377 .seh_pushreg %<reg>
407 movaps %<xmm reg>, -MMM(%rbp)
409 .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
413 movaps %<xmm reg>, KKK(%rsp)
415 .seh_savexmm %<xmm reg>, KKK
425 .cfi_offset %<reg>, (offset from %rbp)
429 .cfi_offset %<reg>, (offset from %rsp)
529 // REG < 64 => DW_CFA_offset + Reg
612 unsigned Reg = MBBI->getOperand(0).getReg();
627 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg)).addImm(Reg).setMIFlag(
783 unsigned Reg = Info.getReg();
784 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
786 assert(X86::FR64RegClass.contains(Reg) && "Unexpected register class");
792 .addImm(Reg)
1119 unsigned Reg = CSI[i - 1].getReg();
1121 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1135 unsigned Reg = CSI[i - 1].getReg();
1136 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1139 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
1166 unsigned Reg = CSI[i - 1].getReg();
1168 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1171 MBB.addLiveIn(Reg);
1173 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1180 unsigned Reg = CSI[i-1].getReg();
1181 if (X86::GR64RegClass.contains(Reg) ||
1182 X86::GR32RegClass.contains(Reg))
1185 MBB.addLiveIn(Reg);
1186 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1188 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
1213 unsigned Reg = CSI[i].getReg();
1214 if (X86::GR64RegClass.contains(Reg) ||
1215 X86::GR32RegClass.contains(Reg))
1218 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1219 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
1225 unsigned Reg = CSI[i].getReg();
1226 if (!X86::GR64RegClass.contains(Reg) &&
1227 !X86::GR32RegClass.contains(Reg))
1230 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
