Lines Matching defs:V2
74 SDValue V2);
180 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
184 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
187 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
191 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
3415 SDValue V1, SDValue V2, unsigned TargetMask,
3422 return DAG.getNode(Opc, dl, VT, V1, V2,
3428 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3440 return DAG.getNode(Opc, dl, VT, V1, V2);
4286 /// the second half of V2.
4779 /// half of V2 (and in order).
4834 /// half of V2 (and in order). And since V1 will become the source of the
4836 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4843 // Is V2 is a vector load, don't do this transformation. We will try to use
4845 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4866 SDValue V2 = N->getOperand(1);
4871 unsigned Opc = V2.getOpcode();
4872 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4875 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4960 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4961 /// that point to V2 points to its first element.
4973 SDValue V2) {
4979 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4984 SDValue V2) {
4991 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4996 SDValue V2) {
5003 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5094 /// element of V2 is swizzled into the zero/undef vector, landing at element
5096 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5100 MVT VT = V2.getSimpleValueType();
5102 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5106 // If this is the insertion idx, put the low elt of V2 here.
5108 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5331 // vector_shuffle V1, V2 <1, 2, 3, X>
5364 // 0 { A, B, X, X } = V2
5366 // vector_shuffle V1, V2 <X, X, 4, 5>
6712 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6714 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6856 SDValue V2 = Op.getOperand(1);
6859 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6866 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6869 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6957 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
6963 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
6966 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
6979 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
6989 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
6995 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
6998 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7019 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7021 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7029 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7035 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7040 SDValue LowV = V1, HighV = V2;
7061 // Handles all the cases where we have a single V2 element and an undef.
7068 // Handle the case where the V2 element ends up adjacent to a V1 element.
7072 V2 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V2, V1,
7078 LowV = V2;
7081 HighV = V2;
7083 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7084 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7088 // Handle the easy case where we have V1 in the low lanes and V2 in the
7093 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7098 // V2.
7103 V1 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V2,
7123 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7129 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7149 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7481 SDValue V2,
7486 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7567 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
7570 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
7581 DL, MVT::v8i16, V1, V2),
7597 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7603 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7625 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
7644 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
7645 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
7658 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
7659 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
7674 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7680 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
7800 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
7801 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
7830 SDValue V1, V2;
7843 // This will be a single vector shuffle instead of a blend so nuke V2.
7844 V2 = DAG.getUNDEF(MVT::v8i16);
7855 // V2 so that we can blend them as i16s.
7858 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7862 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
7863 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
7868 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
7880 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7885 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
7887 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
7889 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
7891 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
7893 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
7895 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
7923 SDValue V2 = Op.getOperand(1);
7931 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7951 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
7967 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
7969 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
7982 // V2. This allows us to match the shuffle pattern strictly on how many
7987 // When the number of V1 and V2 elements are the same, try to minimize the
7988 // number of uses of V2 in the low half of the vector.
8002 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
8071 SDValue V2 = SVOp->getOperand(1);
8082 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
8085 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
8152 SDValue V2 = SVOp->getOperand(1);
8161 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
8227 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
8262 // If we've eliminated the use of V2, and the new mask is a pshuflw or
8289 // shuffle mask element to zero out elements that come from V2 in the V1
8290 // mask, and elements that come from V1 in the V2 mask, so that the two
8300 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
8301 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8374 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
8391 SDValue V2 = SVOp->getOperand(1);
8394 if (V2.getOpcode() != ISD::UNDEF)
8410 SDValue V2 = SVOp->getOperand(1);
8431 // elements that come from V2 in the first mask, and V1 in the second mask
8445 if (V2.getOpcode() == ISD::UNDEF ||
8446 ISD::isBuildVectorAllZeros(V2.getNode()))
8457 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
8460 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8467 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
8481 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
8482 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
8539 SDValue V2 = SVOp->getOperand(1);
8543 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
8545 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
8557 V1 = V2;
8604 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
8605 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
8761 SDValue V2 = SVOp->getOperand(1);
8797 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
8822 std::swap(V1, V2);
8825 // Find the element from V2.
8839 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
8846 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
8857 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
8889 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
8890 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
8927 SDValue V2 = Op.getOperand(1);
8933 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
8939 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
8945 SDValue V2 = Op.getOperand(1);
8951 if (V2.getOpcode() == ISD::UNDEF)
8952 V2 = V1;
8955 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
8961 SDValue V2 = Op.getOperand(1);
8965 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
8971 // Trivial case, when V2 comes from a load.
8972 if (MayFoldVectorLoad(V2))
8986 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
8991 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
9004 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
9005 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
9011 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
9046 SDValue V2 = SVOp->getOperand(1);
9060 To = V2;
9065 "More than one element from V1 and from V2, or no elements from one "
9068 From = V2;
9121 SDValue V2 = Op.getOperand(1);
9126 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
9199 SDValue V2 = Op.getOperand(1);
9226 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
9252 SDValue V2 = Op.getOperand(1);
9257 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9346 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
9365 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
9368 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
9371 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
9392 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
9409 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
9416 std::swap(V1, V2);
9425 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
9428 return getMOVL(DAG, dl, VT, V2, V1);
9432 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9435 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9438 // Normalize mask so all entries that point to V2 points to its first
9444 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9446 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9453 std::swap(V1, V2);
9457 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9460 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9493 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
9521 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
9527 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
9551 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
15736 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
15759 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
15762 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18335 SDValue V2 = SVOp->getOperand(1);
18340 V2.getOpcode() == ISD::CONCAT_VECTORS) {
18351 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
18352 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
18356 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20454 SDValue V2 = N->getOperand(1);
20459 ISD::isBuildVectorAllOnes(V2.getNode()))
