Lines Matching full:fadd
338 // 64-bit FILD followed by conditional FADD for other targets.
809 setOperationAction(ISD::FADD, VT, Expand);
926 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
965 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
1148 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1161 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1350 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1357 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1568 setTargetDAGCombine(ISD::FADD);
6095 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6254 unsigned NextExpectedOpcode = ISD::FADD;
6307 // FADD is commutable. Try to commute the operands
6389 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6410 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6411 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6475 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
10819 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
10975 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
18761 // (shuffle (FADD A, B), (FSUB A, B), Mask) ->
18762 // (shuffle (FSUB A, -B), (FADD A, -B), Mask)
18774 N0->getOpcode() == ISD::FADD && N1->getOpcode() == ISD::FSUB &&
18775 // Operands to the FADD and FSUB must be the same.
18778 // FADD is commutable. See if by commuting the operands of the FADD
18797 SDValue Add = DAG.getNode(ISD::FADD, dl, VT, Op0, Op1);
18839 case ISD::FADD :
21990 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
