Lines Matching refs:getOpcode
1466 switch (MI.getOpcode()) {
1486 switch (MI.getOpcode()) {
1590 if (isFrameLoadOpcode(MI->getOpcode()))
1598 if (isFrameLoadOpcode(MI->getOpcode())) {
1611 if (isFrameStoreOpcode(MI->getOpcode()))
1620 if (isFrameStoreOpcode(MI->getOpcode())) {
1641 if (DefMI->getOpcode() != X86::MOVPC32r)
1652 switch (MI->getOpcode()) {
1814 unsigned Opc = Orig->getOpcode();
2079 unsigned MIOpc = MI->getOpcode();
2362 switch (MI->getOpcode()) {
2371 switch (MI->getOpcode()) {
2407 switch (MI->getOpcode()) {
2473 switch (MI->getOpcode()) {
2782 if (I->getOpcode() == X86::JMP_4) {
2812 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
2909 if (I->getOpcode() != X86::JMP_4 &&
2910 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
3356 switch (MI->getOpcode()) {
3434 if (((FlagI->getOpcode() == X86::CMP64rr &&
3435 OI->getOpcode() == X86::SUB64rr) ||
3436 (FlagI->getOpcode() == X86::CMP32rr &&
3437 OI->getOpcode() == X86::SUB32rr)||
3438 (FlagI->getOpcode() == X86::CMP16rr &&
3439 OI->getOpcode() == X86::SUB16rr)||
3440 (FlagI->getOpcode() == X86::CMP8rr &&
3441 OI->getOpcode() == X86::SUB8rr)) &&
3448 if (((FlagI->getOpcode() == X86::CMP64ri32 &&
3449 OI->getOpcode() == X86::SUB64ri32) ||
3450 (FlagI->getOpcode() == X86::CMP64ri8 &&
3451 OI->getOpcode() == X86::SUB64ri8) ||
3452 (FlagI->getOpcode() == X86::CMP32ri &&
3453 OI->getOpcode() == X86::SUB32ri) ||
3454 (FlagI->getOpcode() == X86::CMP32ri8 &&
3455 OI->getOpcode() == X86::SUB32ri8) ||
3456 (FlagI->getOpcode() == X86::CMP16ri &&
3457 OI->getOpcode() == X86::SUB16ri) ||
3458 (FlagI->getOpcode() == X86::CMP16ri8 &&
3459 OI->getOpcode() == X86::SUB16ri8) ||
3460 (FlagI->getOpcode() == X86::CMP8ri &&
3461 OI->getOpcode() == X86::SUB8ri)) &&
3471 switch (MI->getOpcode()) {
3559 switch (MI->getOpcode()) {
3585 switch (CmpInstr->getOpcode()) {
3605 switch (CmpInstr->getOpcode()) {
3703 if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
3747 OldCC = getCondFromBranchOpc(Instr.getOpcode());
3749 OldCC = getCondFromSETOpc(Instr.getOpcode());
3753 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
3967 switch (MI->getOpcode()) {
4082 (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r)) {
4092 if (MI->getOpcode() == X86::ADD32ri &&
4107 if (MI->getOpcode() == X86::MOV32r0) {
4126 OpcodeTablePtr->find(MI->getOpcode());
4223 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
4293 if (!hasUndefRegUpdate(MI->getOpcode()))
4344 hasPartialRegUpdate(MI->getOpcode()))
4358 switch (MI->getOpcode()) {
4397 hasPartialRegUpdate(MI->getOpcode()))
4405 switch (LoadMI->getOpcode()) {
4425 switch (MI->getOpcode()) {
4444 switch (LoadMI->getOpcode()) {
4475 unsigned Opc = LoadMI->getOpcode();
4499 if ((LoadMI->getOpcode() == X86::MOVSSrm ||
4500 LoadMI->getOpcode() == X86::VMOVSSrm) &&
4506 if ((LoadMI->getOpcode() == X86::MOVSDrm ||
4507 LoadMI->getOpcode() == X86::VMOVSDrm) &&
4530 switch (MI->getOpcode()) {
4550 unsigned Opc = MI->getOpcode();
4584 MemOp2RegOpTable.find(MI->getOpcode());
4662 switch (DataMI->getOpcode()) {
4675 switch (DataMI->getOpcode()) {
4997 switch(Second->getOpcode()) {
5023 switch (First->getOpcode()) {
5276 if (domain && lookup(MI->getOpcode(), domain))
5278 else if (domain && lookupAVX2(MI->getOpcode(), domain))
5287 const uint16_t *table = lookup(MI->getOpcode(), dom);
5291 table = lookupAVX2(MI->getOpcode(), dom);
5394 return isHighLatencyDef(DefMI->getOpcode());
5496 switch (I->getOpcode()) {
