Lines Matching full:src3
133 (ins VR128:$src1, VR128:$src2, VR128:$src3),
135 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
137 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP_4V, VEX_I8IMM;
139 (ins VR128:$src1, i128mem:$src2, VR128:$src3),
141 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
144 VR128:$src3))]>, XOP_4V, VEX_I8IMM;
163 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
165 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
166 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2, imm:$src3))]>,
169 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
171 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
174 imm:$src3))]>, XOP_4V;
189 (ins VR128:$src1, VR128:$src2, VR128:$src3),
191 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
192 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2, VR128:$src3))]>,
195 (ins VR128:$src1, VR128:$src2, i128mem:$src3),
197 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
200 (bitconvert (memopv2i64 addr:$src3))))]>,
203 (ins VR128:$src1, i128mem:$src2, VR128:$src3),
205 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
208 VR128:$src3))]>,
217 (ins VR256:$src1, VR256:$src2, VR256:$src3),
219 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
220 [(set VR256:$dst, (Int VR256:$src1, VR256:$src2, VR256:$src3))]>,
223 (ins VR256:$src1, VR256:$src2, i256mem:$src3),
225 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
228 (bitconvert (memopv4i64 addr:$src3))))]>,
231 (ins VR256:$src1, f256mem:$src2, VR256:$src3),
233 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
236 VR256:$src3))]>,
245 (ins VR128:$src1, VR128:$src2, VR128:$src3, i8imm:$src4),
247 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
249 (Int128 VR128:$src1, VR128:$src2, VR128:$src3, imm:$src4))]>;
251 (ins VR128:$src1, VR128:$src2, f128mem:$src3, i8imm:$src4),
253 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
255 (Int128 VR128:$src1, VR128:$src2, (ld_128 addr:$src3), imm:$src4))]>,
258 (ins VR128:$src1, f128mem:$src2, VR128:$src3, i8imm:$src4),
260 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
262 (Int128 VR128:$src1, (ld_128 addr:$src2), VR128:$src3, imm:$src4))]>;
264 (ins VR256:$src1, VR256:$src2, VR256:$src3, i8imm:$src4),
266 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
268 (Int256 VR256:$src1, VR256:$src2, VR256:$src3, imm:$src4))]>, VEX_L;
270 (ins VR256:$src1, VR256:$src2, f256mem:$src3, i8imm:$src4),
272 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
274 (Int256 VR256:$src1, VR256:$src2, (ld_256 addr:$src3), imm:$src4))]>,
277 (ins VR256:$src1, f256mem:$src2, VR256:$src3, i8imm:$src4),
279 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
281 (Int256 VR256:$src1, (ld_256 addr:$src2), VR256:$src3, imm:$src4))]>,
