Lines Matching full:coerce
3 define i64 @test__builtin_mips_dpa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
7 %1 = bitcast i32 %a1.coerce to <2 x i16>
8 %2 = bitcast i32 %a2.coerce to <2 x i16>
15 define i64 @test__builtin_mips_dps_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
19 %1 = bitcast i32 %a1.coerce to <2 x i16>
20 %2 = bitcast i32 %a2.coerce to <2 x i16>
27 define i64 @test__builtin_mips_mulsa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
31 %1 = bitcast i32 %a1.coerce to <2 x i16>
32 %2 = bitcast i32 %a2.coerce to <2 x i16>
39 define i64 @test__builtin_mips_dpax_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
43 %1 = bitcast i32 %a1.coerce to <2 x i16>
44 %2 = bitcast i32 %a2.coerce to <2 x i16>
51 define i64 @test__builtin_mips_dpsx_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
55 %1 = bitcast i32 %a1.coerce to <2 x i16>
56 %2 = bitcast i32 %a2.coerce to <2 x i16>
63 define i64 @test__builtin_mips_dpaqx_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
67 %1 = bitcast i32 %a1.coerce to <2 x i16>
68 %2 = bitcast i32 %a2.coerce to <2 x i16>
75 define i64 @test__builtin_mips_dpaqx_sa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
79 %1 = bitcast i32 %a1.coerce to <2 x i16>
80 %2 = bitcast i32 %a2.coerce to <2 x i16>
87 define i64 @test__builtin_mips_dpsqx_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
91 %1 = bitcast i32 %a1.coerce to <2 x i16>
92 %2 = bitcast i32 %a2.coerce to <2 x i16>
99 define i64 @test__builtin_mips_dpsqx_sa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
103 %1 = bitcast i32 %a1.coerce to <2 x i16>
104 %2 = bitcast i32 %a2.coerce to <2 x i16>
111 define { i32 } @test__builtin_mips_addu_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
115 %0 = bitcast i32 %a0.coerce to <2 x i16>
116 %1 = bitcast i32 %a1.coerce to <2 x i16>
125 define { i32 } @test__builtin_mips_addu_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
129 %0 = bitcast i32 %a0.coerce to <2 x i16>
130 %1 = bitcast i32 %a1.coerce to <2 x i16>
139 define { i32 } @test__builtin_mips_mulq_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
143 %0 = bitcast i32 %a0.coerce to <2 x i16>
144 %1 = bitcast i32 %a1.coerce to <2 x i16>
153 define { i32 } @test__builtin_mips_subu_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
157 %0 = bitcast i32 %a0.coerce to <2 x i16>
158 %1 = bitcast i32 %a1.coerce to <2 x i16>
167 define { i32 } @test__builtin_mips_subu_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
171 %0 = bitcast i32 %a0.coerce to <2 x i16>
172 %1 = bitcast i32 %a1.coerce to <2 x i16>
181 define i32 @test__builtin_mips_cmpgdu_eq_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
185 %0 = bitcast i32 %a0.coerce to <4 x i8>
186 %1 = bitcast i32 %a1.coerce to <4 x i8>
193 define i32 @test__builtin_mips_cmpgdu_lt_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
197 %0 = bitcast i32 %a0.coerce to <4 x i8>
198 %1 = bitcast i32 %a1.coerce to <4 x i8>
205 define i32 @test__builtin_mips_cmpgdu_le_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
209 %0 = bitcast i32 %a0.coerce to <4 x i8>
210 %1 = bitcast i32 %a1.coerce to <4 x i8>
217 define { i32 } @test__builtin_mips_precr_qb_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
221 %0 = bitcast i32 %a0.coerce to <2 x i16>
222 %1 = bitcast i32 %a1.coerce to <2 x i16>
255 define { i32 } @test__builtin_mips_shra_qb1(i32 %i0, i32 %a0.coerce) nounwind readnone {
259 %0 = bitcast i32 %a0.coerce to <4 x i8>
268 define { i32 } @test__builtin_mips_shra_r_qb1(i32 %i0, i32 %a0.coerce) nounwind readnone {
272 %0 = bitcast i32 %a0.coerce to <4 x i8>
281 define { i32 } @test__builtin_mips_shra_qb2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind readnone {
285 %0 = bitcast i32 %a0.coerce to <4 x i8>
292 define { i32 } @test__builtin_mips_shra_r_qb2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind readnone {
296 %0 = bitcast i32 %a0.coerce to <4 x i8>
303 define { i32 } @test__builtin_mips_shrl_ph1(i32 %i0, i32 %a0.coerce) nounwind readnone {
307 %0 = bitcast i32 %a0.coerce to <2 x i16>
316 define { i32 } @test__builtin_mips_shrl_ph2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind readnone {
320 %0 = bitcast i32 %a0.coerce to <2 x i16>
327 define { i32 } @test__builtin_mips_absq_s_qb1(i32 %i0, i32 %a0.coerce) nounwind {
331 %0 = bitcast i32 %a0.coerce to <4 x i8>
340 define { i32 } @test__builtin_mips_mul_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
344 %0 = bitcast i32 %a0.coerce to <2 x i16>
345 %1 = bitcast i32 %a1.coerce to <2 x i16>
354 define { i32 } @test__builtin_mips_mul_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
358 %0 = bitcast i32 %a0.coerce to <2 x i16>
359 %1 = bitcast i32 %a1.coerce to <2 x i16>
388 define { i32 } @test__builtin_mips_adduh_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {
392 %0 = bitcast i32 %a0.coerce to <4 x i8>
393 %1 = bitcast i32 %a1.coerce to <4 x i8>
402 define { i32 } @test__builtin_mips_adduh_r_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {
406 %0 = bitcast i32 %a0.coerce to <4 x i8>
407 %1 = bitcast i32 %a1.coerce to <4 x i8>
416 define { i32 } @test__builtin_mips_subuh_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {
420 %0 = bitcast i32 %a0.coerce to <4 x i8>
421 %1 = bitcast i32 %a1.coerce to <4 x i8>
430 define { i32 } @test__builtin_mips_subuh_r_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {
434 %0 = bitcast i32 %a0.coerce to <4 x i8>
435 %1 = bitcast i32 %a1.coerce to <4 x i8>
444 define { i32 } @test__builtin_mips_addqh_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {
448 %0 = bitcast i32 %a0.coerce to <2 x i16>
449 %1 = bitcast i32 %a1.coerce to <2 x i16>
458 define { i32 } @test__builtin_mips_addqh_r_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {
462 %0 = bitcast i32 %a0.coerce to <2 x i16>
463 %1 = bitcast i32 %a1.coerce to <2 x i16>
492 define { i32 } @test__builtin_mips_subqh_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {
496 %0 = bitcast i32 %a0.coerce to <2 x i16>
497 %1 = bitcast i32 %a1.coerce to <2 x i16>
506 define { i32 } @test__builtin_mips_subqh_r_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {
510 %0 = bitcast i32 %a0.coerce to <2 x i16>
511 %1 = bitcast i32 %a1.coerce to <2 x i16>
