Lines Matching full:invec
5 define <16 x i16> @test_sllw_1(<16 x i16> %InVec) {
7 %shl = shl <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
15 define <16 x i16> @test_sllw_2(<16 x i16> %InVec) {
17 %shl = shl <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
25 define <16 x i16> @test_sllw_3(<16 x i16> %InVec) {
27 %shl = shl <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
35 define <8 x i32> @test_slld_1(<8 x i32> %InVec) {
37 %shl = shl <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
45 define <8 x i32> @test_slld_2(<8 x i32> %InVec) {
47 %shl = shl <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
65 define <8 x i32> @test_slld_3(<8 x i32> %InVec) {
67 %shl = shl <8 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
75 define <4 x i64> @test_sllq_1(<4 x i64> %InVec) {
77 %shl = shl <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0>
85 define <4 x i64> @test_sllq_2(<4 x i64> %InVec) {
87 %shl = shl <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
95 define <4 x i64> @test_sllq_3(<4 x i64> %InVec) {
97 %shl = shl <4 x i64> %InVec, <i64 63, i64 63, i64 63, i64 63>
107 define <16 x i16> @test_sraw_1(<16 x i16> %InVec) {
109 %shl = ashr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
117 define <16 x i16> @test_sraw_2(<16 x i16> %InVec) {
119 %shl = ashr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
127 define <16 x i16> @test_sraw_3(<16 x i16> %InVec) {
129 %shl = ashr <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
137 define <8 x i32> @test_srad_1(<8 x i32> %InVec) {
139 %shl = ashr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
147 define <8 x i32> @test_srad_2(<8 x i32> %InVec) {
149 %shl = ashr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
157 define <8 x i32> @test_srad_3(<8 x i32> %InVec) {
159 %shl = ashr <8 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
169 define <16 x i16> @test_srlw_1(<16 x i16> %InVec) {
171 %shl = lshr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
179 define <16 x i16> @test_srlw_2(<16 x i16> %InVec) {
181 %shl = lshr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
189 define <16 x i16> @test_srlw_3(<16 x i16> %InVec) {
191 %shl = lshr <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
199 define <8 x i32> @test_srld_1(<8 x i32> %InVec) {
201 %shl = lshr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
209 define <8 x i32> @test_srld_2(<8 x i32> %InVec) {
211 %shl = lshr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
219 define <8 x i32> @test_srld_3(<8 x i32> %InVec) {
221 %shl = lshr <8 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
229 define <4 x i64> @test_srlq_1(<4 x i64> %InVec) {
231 %shl = lshr <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0>
239 define <4 x i64> @test_srlq_2(<4 x i64> %InVec) {
241 %shl = lshr <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
249 define <4 x i64> @test_srlq_3(<4 x i64> %InVec) {
251 %shl = lshr <4 x i64> %InVec, <i64 63, i64 63, i64 63, i64 63>
