Lines Matching full:invec
5 define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
7 %shl = shl <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
15 define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
17 %shl = shl <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
25 define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
27 %shl = shl <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
35 define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
37 %shl = shl <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
45 define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
47 %shl = shl <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
55 define <4 x i32> @test_slld_3(<4 x i32> %InVec) {
57 %shl = shl <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31>
65 define <2 x i64> @test_sllq_1(<2 x i64> %InVec) {
67 %shl = shl <2 x i64> %InVec, <i64 0, i64 0>
75 define <2 x i64> @test_sllq_2(<2 x i64> %InVec) {
77 %shl = shl <2 x i64> %InVec, <i64 1, i64 1>
85 define <2 x i64> @test_sllq_3(<2 x i64> %InVec) {
87 %shl = shl <2 x i64> %InVec, <i64 63, i64 63>
97 define <8 x i16> @test_sraw_1(<8 x i16> %InVec) {
99 %shl = ashr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
107 define <8 x i16> @test_sraw_2(<8 x i16> %InVec) {
109 %shl = ashr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
117 define <8 x i16> @test_sraw_3(<8 x i16> %InVec) {
119 %shl = ashr <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
127 define <4 x i32> @test_srad_1(<4 x i32> %InVec) {
129 %shl = ashr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
137 define <4 x i32> @test_srad_2(<4 x i32> %InVec) {
139 %shl = ashr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
147 define <4 x i32> @test_srad_3(<4 x i32> %InVec) {
149 %shl = ashr <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31>
159 define <8 x i16> @test_srlw_1(<8 x i16> %InVec) {
161 %shl = lshr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
169 define <8 x i16> @test_srlw_2(<8 x i16> %InVec) {
171 %shl = lshr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
179 define <8 x i16> @test_srlw_3(<8 x i16> %InVec) {
181 %shl = lshr <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
189 define <4 x i32> @test_srld_1(<4 x i32> %InVec) {
191 %shl = lshr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
199 define <4 x i32> @test_srld_2(<4 x i32> %InVec) {
201 %shl = lshr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
209 define <4 x i32> @test_srld_3(<4 x i32> %InVec) {
211 %shl = lshr <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31>
219 define <2 x i64> @test_srlq_1(<2 x i64> %InVec) {
221 %shl = lshr <2 x i64> %InVec, <i64 0, i64 0>
229 define <2 x i64> @test_srlq_2(<2 x i64> %InVec) {
231 %shl = lshr <2 x i64> %InVec, <i64 1, i64 1>
239 define <2 x i64> @test_srlq_3(<2 x i64> %InVec) {
241 %shl = lshr <2 x i64> %InVec, <i64 63, i64 63>
