Lines Matching refs:WriteMask
585 uint writemask = inst->Dst[0].Register.WriteMask;
586 if (writemask == TGSI_WRITEMASK_X ||
587 writemask == TGSI_WRITEMASK_Y ||
588 writemask == TGSI_WRITEMASK_Z ||
589 writemask == TGSI_WRITEMASK_W ||
590 writemask == TGSI_WRITEMASK_NONE) {
606 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1908 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1987 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2059 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2088 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2200 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2263 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2424 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2450 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2467 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2475 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2500 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2517 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2526 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2548 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2558 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2582 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2606 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2631 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2660 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2682 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2710 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2721 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2740 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2747 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2756 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
2762 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2766 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2771 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2774 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2788 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XZ) {
2797 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YW) {
2806 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2809 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2812 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2815 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2826 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2851 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2856 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2861 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2867 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2903 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2906 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2909 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2912 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2924 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2929 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2932 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2936 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2939 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2942 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2945 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2960 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2963 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2968 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2971 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2984 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2988 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2992 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2996 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3008 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
3010 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3021 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3026 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3030 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
