Lines Matching refs:Stencil
56 * Since the HiZ, depth, and stencil buffers all use the same "depth
95 /* Stencil buffer uses 64x64 tiles. */
100 /* Gen7 doesn't support packed depth/stencil */
114 /* _NEW_STENCIL: enable stencil buffer writes */
115 dw1 |= ((ctx->Stencil.WriteMask != 0) << 27);
195 ((stencil_mt != NULL && ctx->Stencil.WriteMask != 0) << 27) |
240 /* Note: We can't compute the stencil offset using
241 * intel_region_get_aligned_offset(), because the stencil region claims
250 /* The stencil buffer has quirky pitch requirements. From the Graphics
251 * BSpec: vol2a.11 3D Pipeline Windower > Early Depth/Stencil Processing
252 * > Depth/Stencil Buffer State > 3DSTATE_STENCIL_BUFFER [DevIVB+],
256 * the stencil buffer is stored with two rows interleaved.
