Lines Matching refs:XMM_L
3433 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3435 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3436 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3437 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3440 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3441 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3449 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3450 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3475 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3476 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3477 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3478 offsetof(CPUX86State,xmm_regs[rm].XMM_L(2)));
3480 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3481 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3482 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3483 offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3515 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3516 offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
3517 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3518 offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
3520 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3521 offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3522 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3523 offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3549 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3592 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3596 gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
3597 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3640 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3642 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
3768 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3906 offsetof(XMMReg, XMM_L(0)));
4019 xmm_regs[reg].XMM_L(val & 3)));
4043 xmm_regs[reg].XMM_L(val & 3)));
4063 .XMM_L((val >> 6) & 3)));
4071 .XMM_L((val >> 4) & 3)));
4075 xmm_regs[reg].XMM_L(0)));
4079 xmm_regs[reg].XMM_L(1)));
4083 xmm_regs[reg].XMM_L(2)));
4087 xmm_regs[reg].XMM_L(3)));
4099 xmm_regs[reg].XMM_L(val & 3)));
4177 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
