Lines Matching refs:rT
2989 Rm is insn[20:16]. Rn is insn[9:5]. Rt is insn[4:0]. Log2 of
3191 sz 111 00000 0 imm9 01 Rn Rt STR Rt, [Xn|SP], #simm9
3192 sz 111 00001 0 imm9 01 Rn Rt LDR Rt, [Xn|SP], #simm9
3195 sz 111 00000 0 imm9 11 Rn Rt STR Rt, [Xn|SP, #simm9]!
3196 sz 111 00001 0 imm9 11 Rn Rt LDR Rt, [Xn|SP, #simm9]!
3199 sz 111 00000 0 imm9 00 Rn Rt STR Rt, [Xn|SP, #simm9]
3200 sz 111 00001 0 imm9 00 Rn Rt LDR Rt, [Xn|SP, #simm9]
3204 The case 'wback && Rn == Rt && Rt != 31' is disallowed. In the
3206 Rt. In the store case the reason is unclear, but the spec
3423 00 011 000 imm19 Rt LDR Wt, [PC + sxTo64(imm19 << 2)]
3424 01 011 000 imm19 Rt LDR Xt, [PC + sxTo64(imm19 << 2)]
3425 10 011 000 imm19 Rt LDRSW Xt, [PC + sxTo64(imm19 << 2)]
3426 11 011 000 imm19 Rt prefetch [PC + sxTo64(imm19 << 2)]
3431 UInt rT = INSN(4,0);
3435 putIReg64orZR(rT, loadLE(Ity_I64, mkU64(ea)));
3437 putIReg32orZR(rT, loadLE(Ity_I32, mkU64(ea)));
3439 DIP("ldr %s, 0x%llx (literal)\n", nameIRegOrZR(bX == 1, rT), ea);
3446 11 111000011 Rm option S 10 Rn Rt LDR Xt, [Xn|SP, R<m>{ext/sh}]
3447 10 111000011 Rm option S 10 Rn Rt LDR Wt, [Xn|SP, R<m>{ext/sh}]
3448 01 111000011 Rm option S 10 Rn Rt LDRH Wt, [Xn|SP, R<m>{ext/sh}]
3449 00 111000011 Rm option S 10 Rn Rt LDRB Wt, [Xn|SP, R<m>{ext/sh}]
3451 11 111000001 Rm option S 10 Rn Rt STR Xt, [Xn|SP, R<m>{ext/sh}]
3452 10 111000001 Rm option S 10 Rn Rt STR Wt, [Xn|SP, R<m>{ext/sh}]
3453 01 111000001 Rm option S 10 Rn Rt STRH Wt, [Xn|SP, R<m>{ext/sh}]
3454 00 111000001 Rm option S 10 Rn Rt STRB Wt, [Xn|SP, R<m>{ext/sh}]
3513 01 111 001 1x imm12 n t LDRSH Rt, [Xn|SP, #pimm12 * 2]
3514 00 111 001 1x imm12 n t LDRSB Rt, [Xn|SP, #pimm12 * 1]
3516 Rt is Wt when x==1, Xt when x==0
3575 00 111 000 1x 0 imm9 01 n t LDRSB Rt, [Xn|SP], #simm9
3576 01 111 000 1x 0 imm9 01 n t LDRSH Rt, [Xn|SP], #simm9
3580 00 111 000 1x 0 imm9 11 n t LDRSB Rt, [Xn|SP, #simm9]!
3581 01 111 000 1x 0 imm9 11 n t LDRSH Rt, [Xn|SP, #simm9]!
3584 Rt is Wt when x==1, Xt when x==0
3659 00 111 000 1x 0 imm9 00 n t LDURSB Rt, [Xn|SP, #simm9]
3660 01 111 000 1x 0 imm9 00 n t LDURSH Rt, [Xn|SP, #simm9]
3663 Rt is Wt when x==1, Xt when x==0
3861 00 111100 011 Rm option S 10 Rn Rt LDR Bt, [Xn|SP, R<m>{ext/sh}]
3862 01 111100 011 Rm option S 10 Rn Rt LDR Ht, [Xn|SP, R<m>{ext/sh}]
3863 10 111100 011 Rm option S 10 Rn Rt LDR St, [Xn|SP, R<m>{ext/sh}]
3864 11 111100 011 Rm option S 10 Rn Rt LDR Dt, [Xn|SP, R<m>{ext/sh}]
3865 00 111100 111 Rm option S 10 Rn Rt LDR Qt, [Xn|SP, R<m>{ext/sh}]
3867 00 111100 001 Rm option S 10 Rn Rt STR Bt, [Xn|SP, R<m>{ext/sh}]
3868 01 111100 001 Rm option S 10 Rn Rt STR Ht, [Xn|SP, R<m>{ext/sh}]
3869 10 111100 001 Rm option S 10 Rn Rt STR St, [Xn|SP, R<m>{ext/sh}]
3870 11 111100 001 Rm option S 10 Rn Rt STR Dt, [Xn|SP, R<m>{ext/sh}]
3871 00 111100 101 Rm option S 10 Rn Rt STR Qt, [Xn|SP, R<m>{ext/sh}]
3935 10 1110001 01 Rm opt S 10 Rn Rt LDRSW Xt, [Xn|SP, R<m>{ext/sh}]
3937 01 1110001 01 Rm opt S 10 Rn Rt LDRSH Xt, [Xn|SP, R<m>{ext/sh}]
3938 01 1110001 11 Rm opt S 10 Rn Rt LDRSH Wt, [Xn|SP, R<m>{ext/sh}]
3940 00 1110001 01 Rm opt S 10 Rn Rt LDRSB Xt, [Xn|SP, R<m>{ext/sh}]
3941 00 1110001 11 Rm opt S 10 Rn Rt LDRSB Wt, [Xn|SP, R<m>{ext/sh}]
4443 sz 001000 010 11111 0 11111 n t LDX{R,RH,RB} Rt, [Xn|SP]
4444 sz 001000 010 11111 1 11111 n t LDAX{R,RH,RB} Rt, [Xn|SP]
4445 sz 001000 000 s 0 11111 n t STX{R,RH,RB} Ws, Rt, [Xn|SP]
4446 sz 001000 000 s 1 11111 n t STLX{R,RH,RB} Ws, Rt, [Xn|SP]
4500 sz 001000 110 11111 1 11111 n t LDAR<sz> Rt, [Xn|SP]
4501 sz 001000 100 11111 1 11111 n t STLR<sz> Rt, [Xn|SP]
4643 /* sf 011 010 1 imm19 Rt CBNZ Xt|Wt, (PC + sxTo64(imm19 << 2))
4644 sf 011 010 0 imm19 Rt CBZ Xt|Wt, (PC + sxTo64(imm19 << 2))
4650 UInt rT = INSN(4,0);
4655 getIReg64orZR(rT), mkU64(0));
4658 getIReg32orZR(rT), mkU32(0));
4668 bIfZ ? "" : "n", nameIRegOrZR(is64, rT),
4720 0xD51BD0 010 Rt MSR tpidr_el0, rT
4721 0xD53BD0 010 Rt MRS rT, tpidr_el0
4737 0xD51B44 000 Rt MSR fpcr, rT
4738 0xD53B44 000 Rt MSR rT, fpcr
4754 0xD51B44 001 Rt MSR fpsr, rT
4755 0xD53B44 001 Rt MSR rT, fpsr
4771 D51B42 000 Rt MSR nzcv, rT
4772 D53B42 000 Rt MRS rT, nzcv
4795 D5 3B 00 111 Rt MRS rT, dczid_el0
4808 D5 3B 00 001 Rt MRS rT, dczid_el0
4831 /* D5 0B 75 001 Rt ic ivau, rT
4837 /* Round the requested address, in rT, down to the start of the
4859 /* D5 0B 7B 001 Rt dc cvau, rT
4868 /* Round the requested address, in rT, down to the start of the
