Lines Matching defs:shift
1404 Int shift[6];
1416 shift[idx] = 1 << idx;
1432 binop(Iop_Shr32, mkexpr(old), mkU8(shift[i])),
1444 shift[i] = 1 << i;
1459 binop( Iop_Shr64, mkexpr( old ), mkU8( shift[i] ) ),
1471 Int i, shift[6];
1482 shift[i] = 1 << i;
1498 binop(Iop_Shr32, mkexpr(old), mkU8(shift[i])),
1512 binop(Iop_Shr32, mkexpr(old), mkU8(shift[i])),
1542 because otherwise the Shr is a shift by the word size when
2323 /* The shift amount is guaranteed to be in 0 .. 63 inclusive.
2326 /* This term valid for shift amount < 32 only */
2341 /* shift amt > 31 ? */
2352 0. Since the shift amount is known to be in the range
2442 /* The shift amount is guaranteed to be in 0 .. 31 inclusive.
2445 /* This term valid for shift amount < 31 only */
2461 /* shift amt > 31 ? */
2472 Since the shift amount is known to be in the range 0 .. 31
2496 /* The shift amount is guaranteed to be in 0 .. 63 inclusive.
2499 /* This term valid for shift amount < 63 only */
2515 /* shift amt > 63 ? */
2527 Since the shift amount is known to be in the range 0 .. 63
4294 * to determine which bit of rB to use for the perm bit, and then we shift
4553 shift left, PPC32 p501 */
4560 unsigned shift right, PPC32 p501 */
4655 unsigned shift-right by n */
4672 shift-left by n */
5292 Int i, shift = 24;
5309 shift = 24;
5311 /* rD |= (8Uto32(*(EA+i))) << shift */
5312 vassert(shift == 0 || shift == 8 || shift == 16 || shift == 24);
5327 mkU8(toUChar(shift))
5333 shift -= 8;
5343 Int i, shift = 24;
5359 shift = 24;
5361 /* *(EA+i) = 32to8(rS >> shift) */
5362 vassert(shift == 0 || shift == 8 || shift == 16 || shift == 24);
5368 mkU8(toUChar(shift))))
5370 shift -= 8;
6372 Integer Shift Instructions
6402 case 0x018: { // slw (Shift Left Word, PPC32 p505)
6426 case 0x318: { // sraw (Shift Right Alg Word, PPC32 p506)
6455 case 0x338: // srawi (Shift Right Alg Word Immediate, PPC32 p507)
6476 case 0x218: // srw (Shift Right Word, PPC32 p508)
6503 case 0x01B: // sld (Shift Left DWord, PPC64 p568)
6525 case 0x31A: { // srad (Shift Right Alg DWord, PPC64 p570)
6564 case 0x21B: // srd (Shift Right DWord, PPC64 p574)
9188 * bits in the highest order nibble (field 0) and shift right
9406 #define DIGIT1_SHR 4 // shift digit 1 to bottom 4 bits
9407 #define DIGIT2_SHR 8 // shift digit 2 to bottom 4 bits
9973 /* DFP 64-bit logical shift instructions */
10010 /* Quad DFP logical shift instructions */
10652 * specific setup. Once the value of the exponents, the G-field shift
15304 case 0x8: // xxsldwi (VSX Shift Left Double by Word Immediate)
15428 case 0x006: { // lvsl (Load Vector for Shift Left, AV p123)
15462 case 0x026: { // lvsr (Load Vector for Shift Right, AV p125)
16635 AltiVec Shift/Rotate Instructions
16679 /* Shift Left */
16680 case 0x104: // vslb (Shift Left Integer B, AV p240)
16685 case 0x144: // vslh (Shift Left Integer HW, AV p242)
16690 case 0x184: // vslw (Shift Left Integer W, AV p244)
16695 case 0x5C4: // vsld (Shift Left Integer Double Word)
16700 case 0x1C4: { // vsl (Shift Left, AV p239)
16710 case 0x40C: { // vslo (Shift Left by Octet, AV p243)
16722 /* Shift Right */
16723 case 0x204: // vsrb (Shift Right B, AV p256)
16728 case 0x244: // vsrh (Shift Right HW, AV p257)
16733 case 0x284: // vsrw (Shift Right W, AV p259)
16738 case 0x2C4: { // vsr (Shift Right, AV p251)
16748 case 0x304: // vsrab (Shift Right Alg B, AV p253)
16753 case 0x344: // vsrah (Shift Right Alg HW, AV p254)
16758 case 0x384: // vsraw (Shift Right Alg W, AV p255)
16763 case 0x3C4: // vsrad (Shift Right Alg Double Word)
16768 case 0x44C: { // vsro (Shift Right by Octet, AV p258)
16779 case 0x6C4: // vsrd (Shift Right Double Word)
16861 case 0x2C: // vsldoi (Shift Left Double by Octet Imm, AV p241)
17952 // finally, just shift gt,lt to correct position
18810 case 0x42: // dscli, DFP shift left
18811 case 0x62: // dscri, DFP shift right
19186 case 0x42: // dscli, DFP shift left
19187 case 0x62: // dscri, DFP shift right
19348 /* Integer Shift Instructions */
19354 /* 64bit Integer Shift Instructions */
19684 /* AV Rotate, Shift */
