Lines Matching refs:Addr
62 Addr memline, iaddr;
109 * - Addr CLG_(bb_base) (instruction start address of original BB)
113 Addr CLG_(bb_base);
142 typedef CacheModelResult (*simcall_type)(Addr, UChar);
243 * CacheModelResult cachesim_I1_ref(Addr a, UChar size)
244 * CacheModelResult cachesim_D1_ref(Addr a, UChar size)
284 CacheResult cachesim_ref(cache_t2* c, Addr a, UChar size)
308 VG_(printf)("addr: %lx size: %u blocks: %ld %ld",
316 CacheModelResult cachesim_I1_ref(Addr a, UChar size)
324 CacheModelResult cachesim_D1_ref(Addr a, UChar size)
341 * CacheModelResult cachesim_I1_Read(Addr a, UChar size)
342 * CacheModelResult cachesim_D1_Read(Addr a, UChar size)
343 * CacheModelResult cachesim_D1_Write(Addr a, UChar size)
393 CacheResult cachesim_ref_wb(cache_t2* c, RefType ref, Addr a, UChar size)
416 VG_(printf)("addr: %lx size: %u sets: %d %d", a, size, set1, set2);
424 CacheModelResult cachesim_I1_Read(Addr a, UChar size)
436 CacheModelResult cachesim_D1_Read(Addr a, UChar size)
448 CacheModelResult cachesim_D1_Write(Addr a, UChar size)
494 void prefetch_LL_doref(Addr a)
531 CacheModelResult prefetch_I1_ref(Addr a, UChar size)
540 CacheModelResult prefetch_D1_ref(Addr a, UChar size)
552 CacheModelResult prefetch_I1_Read(Addr a, UChar size)
565 CacheModelResult prefetch_D1_Read(Addr a, UChar size)
578 CacheModelResult prefetch_D1_Write(Addr a, UChar size)
687 static CacheModelResult cacheuse##_##L##_doRead(Addr a, UChar size) \
697 CLG_DEBUG(6,"%s.Acc(Addr %#lx, size %d): Sets [%d/%d]\n", \
827 VG_(printf)("addr: %#lx size: %u sets: %d %d", a, size, set1, set2); \
852 static void update_LL_use(int idx, Addr memline)
883 CacheModelResult cacheuse_LL_access(Addr
940 UInt mask, Addr memline) \
1160 static void log_1I1Dr(InstrInfo* ii, Addr data_addr, Word data_size)
1196 static void log_0I1Dr(InstrInfo* ii, Addr data_addr, Word data_size)
1223 static void log_1I1Dw(InstrInfo* ii, Addr data_addr, Word data_size)
1256 static void log_0I1Dw(InstrInfo* ii, Addr data_addr, Word data_size)
