Lines Matching refs:rd
533 void Assembler::adr(const Register& rd, int imm21) {
534 VIXL_ASSERT(rd.Is64Bits());
535 Emit(ADR | ImmPCRelAddress(imm21) | Rd(rd));
539 void Assembler::adr(const Register& rd, Label* label) {
540 adr(rd, UpdateAndGetByteOffsetTo(label));
544 void Assembler::add(const Register& rd,
547 AddSub(rd, rn, operand, LeaveFlags, ADD);
551 void Assembler::adds(const Register& rd,
554 AddSub(rd, rn, operand, SetFlags, ADD);
565 void Assembler::sub(const Register& rd,
568 AddSub(rd, rn, operand, LeaveFlags, SUB);
572 void Assembler::subs(const Register& rd,
575 AddSub(rd, rn, operand, SetFlags, SUB);
585 void Assembler::neg(const Register& rd, const Operand& operand) {
586 Register zr = AppropriateZeroRegFor(rd);
587 sub(rd, zr, operand);
591 void Assembler::negs(const Register& rd, const Operand& operand) {
592 Register zr = AppropriateZeroRegFor(rd);
593 subs(rd, zr, operand);
597 void Assembler::adc(const Register& rd,
600 AddSubWithCarry(rd, rn, operand, LeaveFlags, ADC);
604 void Assembler::adcs(const Register& rd,
607 AddSubWithCarry(rd, rn, operand, SetFlags, ADC);
611 void Assembler::sbc(const Register& rd,
614 AddSubWithCarry(rd, rn, operand, LeaveFlags, SBC);
618 void Assembler::sbcs(const Register& rd,
621 AddSubWithCarry(rd, rn, operand, SetFlags, SBC);
625 void Assembler::ngc(const Register& rd, const Operand& operand) {
626 Register zr = AppropriateZeroRegFor(rd);
627 sbc(rd, zr, operand);
631 void Assembler::ngcs(const Register& rd, const Operand& operand) {
632 Register zr = AppropriateZeroRegFor(rd);
633 sbcs(rd, zr, operand);
638 void Assembler::and_(const Register& rd,
641 Logical(rd, rn, operand, AND);
645 void Assembler::ands(const Register& rd,
648 Logical(rd, rn, operand, ANDS);
658 void Assembler::bic(const Register& rd,
661 Logical(rd, rn, operand, BIC);
665 void Assembler::bics(const Register& rd,
668 Logical(rd, rn, operand, BICS);
672 void Assembler::orr(const Register& rd,
675 Logical(rd, rn, operand, ORR);
679 void Assembler::orn(const Register& rd,
682 Logical(rd, rn, operand, ORN);
686 void Assembler::eor(const Register& rd,
689 Logical(rd, rn, operand, EOR);
693 void Assembler::eon(const Register& rd,
696 Logical(rd, rn, operand, EON);
700 void Assembler::lslv(const Register& rd,
703 VIXL_ASSERT(rd.size() == rn.size());
704 VIXL_ASSERT(rd.size() == rm.size());
705 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd));
709 void Assembler::lsrv(const Register& rd,
712 VIXL_ASSERT(rd.size() == rn.size());
713 VIXL_ASSERT(rd.size() == rm.size());
714 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd));
718 void Assembler::asrv(const Register& rd,
721 VIXL_ASSERT(rd.size() == rn.size());
722 VIXL_ASSERT(rd.size() == rm.size());
723 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd));
727 void Assembler::rorv(const Register& rd,
730 VIXL_ASSERT(rd.size() == rn.size());
731 VIXL_ASSERT(rd.size() == rm.size());
732 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd));
737 void Assembler::bfm(const Register& rd,
741 VIXL_ASSERT(rd.size() == rn.size());
742 Instr N = SF(rd) >> (kSFOffset - kBitfieldNOffset);
743 Emit(SF(rd) | BFM | N |
744 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
748 void Assembler::sbfm(const Register& rd,
752 VIXL_ASSERT(rd.Is64Bits() || rn.Is32Bits());
753 Instr N = SF(rd) >> (kSFOffset - kBitfieldNOffset);
754 Emit(SF(rd) | SBFM | N |
755 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
759 void Assembler::ubfm(const Register& rd,
763 VIXL_ASSERT(rd.size() == rn.size());
764 Instr N = SF(rd) >> (kSFOffset - kBitfieldNOffset);
765 Emit(SF(rd) | UBFM | N |
766 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
770 void Assembler::extr(const Register& rd,
774 VIXL_ASSERT(rd.size() == rn.size());
775 VIXL_ASSERT(rd.size() == rm.size());
776 Instr N = SF(rd) >> (kSFOffset - kBitfieldNOffset);
777 Emit(SF(rd) | EXTR | N | Rm(rm) | ImmS(lsb, rn.size()) | Rn(rn) | Rd(rd));
781 void Assembler::csel(const Register& rd,
785 ConditionalSelect(rd, rn, rm, cond, CSEL);
789 void Assembler::csinc(const Register& rd,
793 ConditionalSelect(rd, rn, rm, cond, CSINC);
797 void Assembler::csinv(const Register& rd,
801 ConditionalSelect(rd, rn, rm, cond, CSINV);
805 void Assembler::csneg(const Register& rd,
809 ConditionalSelect(rd, rn, rm, cond, CSNEG);
813 void Assembler::cset(const Register &rd, Condition cond) {
815 Register zr = AppropriateZeroRegFor(rd);
816 csinc(rd, zr, zr, InvertCondition(cond));
820 void Assembler::csetm(const Register &rd, Condition cond) {
822 Register zr = AppropriateZeroRegFor(rd);
823 csinv(rd, zr, zr, InvertCondition(cond));
827 void Assembler::cinc(const Register &rd, const Register &rn, Condition cond) {
829 csinc(rd, rn, rn, InvertCondition(cond));
833 void Assembler::cinv(const Register &rd, const Register &rn, Condition cond) {
835 csinv(rd, rn, rn, InvertCondition(cond));
839 void Assembler::cneg(const Register &rd, const Register &rn, Condition cond) {
841 csneg(rd, rn, rn, InvertCondition(cond));
845 void Assembler::ConditionalSelect(const Register& rd,
850 VIXL_ASSERT(rd.size() == rn.size());
851 VIXL_ASSERT(rd.size() == rm.size());
852 Emit(SF(rd) | op | Rm(rm) | Cond(cond) | Rn(rn) | Rd(rd));
872 void Assembler::DataProcessing3Source(const Register& rd,
877 Emit(SF(rd) | op | Rm(rm) | Ra(ra) | Rn(rn) | Rd(rd));
881 void Assembler::mul(const Register& rd,
884 VIXL_ASSERT(AreSameSizeAndType(rd, rn, rm));
885 DataProcessing3Source(rd, rn, rm, AppropriateZeroRegFor(rd), MADD);
889 void Assembler::madd(const Register& rd,
893 DataProcessing3Source(rd, rn, rm, ra, MADD);
897 void Assembler::mneg(const Register& rd,
900 VIXL_ASSERT(AreSameSizeAndType(rd, rn, rm));
901 DataProcessing3Source(rd, rn, rm, AppropriateZeroRegFor(rd), MSUB);
905 void Assembler::msub(const Register& rd,
909 DataProcessing3Source(rd, rn, rm, ra, MSUB);
913 void Assembler::umaddl(const Register& rd,
917 VIXL_ASSERT(rd.Is64Bits() && ra.Is64Bits());
919 DataProcessing3Source(rd, rn, rm, ra, UMADDL_x);
923 void Assembler::smaddl(const Register& rd,
927 VIXL_ASSERT(rd.Is64Bits() && ra.Is64Bits());
929 DataProcessing3Source(rd, rn, rm, ra, SMADDL_x);
933 void Assembler::umsubl(const Register& rd,
937 VIXL_ASSERT(rd.Is64Bits() && ra.Is64Bits());
939 DataProcessing3Source(rd, rn, rm, ra, UMSUBL_x);
943 void Assembler::smsubl(const Register& rd,
947 VIXL_ASSERT(rd.Is64Bits() && ra.Is64Bits());
949 DataProcessing3Source(rd, rn, rm, ra, SMSUBL_x);
953 void Assembler::smull(const Register& rd,
956 VIXL_ASSERT(rd.Is64Bits());
958 DataProcessing3Source(rd, rn, rm, xzr, SMADDL_x);
962 void Assembler::sdiv(const Register& rd,
965 VIXL_ASSERT(rd.size() == rn.size());
966 VIXL_ASSERT(rd.size() == rm.size());
967 Emit(SF(rd) | SDIV | Rm(rm) | Rn(rn) | Rd(rd));
978 void Assembler::udiv(const Register& rd,
981 VIXL_ASSERT(rd.size() == rn.size());
982 VIXL_ASSERT(rd.size() == rm.size());
983 Emit(SF(rd) | UDIV | Rm(rm) | Rn(rn) | Rd(rd));
987 void Assembler::rbit(const Register& rd,
989 DataProcessing1Source(rd, rn, RBIT);
993 void Assembler::rev16(const Register& rd,
995 DataProcessing1Source(rd, rn, REV16);
999 void Assembler::rev32(const Register& rd,
1001 VIXL_ASSERT(rd.Is64Bits());
1002 DataProcessing1Source(rd, rn, REV);
1006 void Assembler::rev(const Register& rd,
1008 DataProcessing1Source(rd, rn, rd.Is64Bits() ? REV_x : REV_w);
1012 void Assembler::clz(const Register& rd,
1014 DataProcessing1Source(rd, rn, CLZ);
1018 void Assembler::cls(const Register& rd,
1020 DataProcessing1Source(rd, rn, CLS);
1168 void Assembler::mov(const Register& rd, const Register& rm) {
1172 if (rd.IsSP() || rm.IsSP()) {
1173 add(rd, rm, 0);
1175 orr(rd, AppropriateZeroRegFor(rd), rm);
1180 void Assembler::mvn(const Register& rd, const Operand& operand) {
1181 orn(rd, AppropriateZeroRegFor(rd), operand);
1220 Emit(FMOV_d_imm | Rd(fd) | ImmFP64(imm));
1227 Emit(FMOV_s_imm | Rd
1231 void Assembler::fmov(const Register& rd, const FPRegister& fn) {
1232 VIXL_ASSERT(rd.size() == fn.size());
1233 FPIntegerConvertOp op = rd.Is32Bits() ? FMOV_ws : FMOV_xd;
1234 Emit(op | Rd(rd) | Rn(fn));
1241 Emit(op | Rd(fd) | Rn(rn));
1247 Emit(FPType(fd) | FMOV | Rd(fd) | Rn(fn));
1421 Emit(FPType(fd) | FCSEL | Rm(fm) | Cond(cond) | Rn(fn) | Rd(fd));
1425 void Assembler::FPConvertToInt(const Register& rd,
1428 Emit(SF(rd) | FPType(fn) | op | Rn(fn) | Rd(rd));
1446 void Assembler::fcvtau(const Register& rd, const FPRegister& fn) {
1447 FPConvertToInt(rd, fn, FCVTAU);
1451 void Assembler::fcvtas(const Register& rd, const FPRegister& fn) {
1452 FPConvertToInt(rd, fn, FCVTAS);
1456 void Assembler::fcvtmu(const Register& rd, const FPRegister& fn) {
1457 FPConvertToInt(rd, fn, FCVTMU);
1461 void Assembler::fcvtms(const Register& rd, const FPRegister& fn) {
1462 FPConvertToInt(rd, fn, FCVTMS);
1466 void Assembler::fcvtnu(const Register& rd, const FPRegister& fn) {
1467 FPConvertToInt(rd, fn, FCVTNU);
1471 void Assembler::fcvtns(const Register& rd, const FPRegister& fn) {
1472 FPConvertToInt(rd, fn, FCVTNS);
1476 void Assembler::fcvtzu(const Register& rd, const FPRegister& fn) {
1477 FPConvertToInt(rd, fn, FCVTZU);
1481 void Assembler::fcvtzs(const Register& rd, const FPRegister& fn) {
1482 FPConvertToInt(rd, fn, FCVTZS);
1490 Emit(SF(rn) | FPType(fd) | SCVTF | Rn(rn) | Rd(fd));
1493 Rd(fd));
1502 Emit(SF(rn) | FPType(fd) | UCVTF | Rn(rn) | Rd(fd));
1505 Rd(fd));
1546 void Assembler::MoveWide(const Register& rd,
1554 VIXL_ASSERT(rd.Is64Bits() || (shift == 0) || (shift == 16));
1566 VIXL_ASSERT(rd.Is64Bits());
1570 VIXL_ASSERT(rd.Is64Bits());
1578 Emit(SF(rd) | MoveWideImmediateFixed | mov_op |
1579 Rd(rd) | ImmMoveWide(imm) | ShiftMoveWide(shift));
1583 void Assembler::AddSub(const Register& rd,
1588 VIXL_ASSERT(rd.size() == rn.size());
1592 Instr dest_reg = (S == SetFlags) ? Rd(rd) : RdSP(rd);
1593 Emit(SF(rd) | AddSubImmediateFixed | op | Flags(S) |
1596 VIXL_ASSERT(operand.reg().size() == rd.size());
1606 if (rn.IsSP() || rd.IsSP()) {
1607 VIXL_ASSERT(!(rd.IsSP() && (S == SetFlags)));
1608 DataProcExtendedRegister(rd, rn, operand.ToExtendedRegister(), S,
1611 DataProcShiftedRegister(rd, rn, operand, S, AddSubShiftedFixed | op);
1615 DataProcExtendedRegister(rd, rn, operand, S, AddSubExtendedFixed | op);
1620 void Assembler::AddSubWithCarry(const Register& rd,
1625 VIXL_ASSERT(rd.size() == rn.size());
1626 VIXL_ASSERT(rd.size() == operand.reg().size());
1628 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) | Rn(rn) | Rd(rd));
1644 void Assembler::Logical(const Register& rd,
1648 VIXL_ASSERT(rd.size() == rn.size());
1651 unsigned reg_size = rd.size();
1655 VIXL_ASSERT(rd.Is64Bits() || is_uint32(immediate));
1660 immediate = rd.Is64Bits() ? ~immediate : (~immediate & kWRegMask);
1666 LogicalImmediate(rd, rn, n, imm_s, imm_r, op);
1673 VIXL_ASSERT(operand.reg().size() == rd.size());
1675 DataProcShiftedRegister(rd, rn, operand, LeaveFlags, dp_op);
1680 void Assembler::LogicalImmediate(const Register& rd,
1686 unsigned reg_size = rd.size();
1687 Instr dest_reg = (op == ANDS) ? Rd(rd) : RdSP(rd);
1688 Emit(SF(rd) | LogicalImmediateFixed | op | BitN(n, reg_size) |
1712 void Assembler::DataProcessing1Source(const Register& rd,
1715 VIXL_ASSERT(rd.size() == rn.size());
1716 Emit(SF(rn) | op | Rn(rn) | Rd(rd));
1723 Emit(FPType(fn) | op | Rn(fn) | Rd(fd));
1733 Emit(FPType(fd) | op | Rm(fm) | Rn(fn) | Rd(fd));
1743 Emit(FPType(fd) | op | Rm(fm) | Rn(fn) | Rd(fd) | Ra(fa));
1747 void Assembler::EmitShift(const Register& rd,
1753 lsl(rd, rn, shift_amount);
1756 lsr(rd, rn, shift_amount);
1759 asr(rd, rn, shift_amount);
1762 ror(rd, rn, shift_amount);
1770 void Assembler::EmitExtendShift(const Register& rd,
1774 VIXL_ASSERT(rd.size() >= rn.size());
1775 unsigned reg_size = rd.size();
1777 Register rn_ = Register(rn.code(), rd.size());
1787 case UXTW: ubfm(rd, rn_, non_shift_bits, high_bit); break;
1790 case SXTW: sbfm(rd, rn_, non_shift_bits, high_bit); break;
1795 lsl(rd, rn_, left_shift);
1802 lsl(rd, rn_, left_shift);
1807 void Assembler::DataProcShiftedRegister(const Register& rd,
1815 Emit(SF(rd) | op | Flags(S) |
1817 Rm(operand.reg()) | Rn(rn) | Rd(rd));
1821 void Assembler::DataProcExtendedRegister(const Register& rd,
1826 Instr dest_reg = (S == SetFlags) ? Rd(rd) : RdSP(rd);
1827 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) |
