Lines Matching refs:rd
49 void MacroAssembler::And(const Register& rd,
53 LogicalMacro(rd, rn, operand, AND);
57 void MacroAssembler::Ands(const Register& rd,
61 LogicalMacro(rd, rn, operand, ANDS);
72 void MacroAssembler::Bic(const Register& rd,
76 LogicalMacro(rd, rn, operand, BIC);
80 void MacroAssembler::Bics(const Register& rd,
84 LogicalMacro(rd, rn, operand, BICS);
88 void MacroAssembler::Orr(const Register& rd,
92 LogicalMacro(rd, rn, operand, ORR);
96 void MacroAssembler::Orn(const Register& rd,
100 LogicalMacro(rd, rn, operand, ORN);
104 void MacroAssembler::Eor(const Register& rd,
108 LogicalMacro(rd, rn, operand, EOR);
112 void MacroAssembler::Eon(const Register& rd,
116 LogicalMacro(rd, rn, operand, EON);
120 void MacroAssembler::LogicalMacro(const Register& rd,
128 unsigned reg_size = rd.size();
129 VIXL_ASSERT(rd.Is64Bits() || is_uint32(immediate));
135 if (rd.Is32Bits()) {
144 Mov(rd, 0);
148 Mov(rd, rn);
156 } else if ((rd.Is64Bits() && (immediate == -1)) ||
157 (rd.Is32Bits() && (immediate == 0xffffffff))) {
160 Mov(rd, rn);
163 Mov(rd, immediate);
166 Mvn(rd, rn);
179 LogicalImmediate(rd, rn, n, imm_s, imm_r, op);
184 if (rd.Is(sp)) {
185 // If rd is the stack pointer we cannot use it as the destination
190 Logical(rd, rn, Operand(temp), op);
194 VIXL_ASSERT(operand.reg().size() <= rd.size());
205 Logical(rd, rn, Operand(temp), op);
209 Logical(rd, rn, operand, op);
214 void MacroAssembler::Mov(const Register& rd,
220 Mov(rd, operand.immediate());
225 EmitShift(rd, operand.reg(), operand.shift(), operand.shift_amount());
229 EmitExtendShift(rd, operand.reg(), operand.extend(),
241 if (!rd.Is(operand.reg()) || (rd.Is32Bits() &&
243 mov(rd, operand.reg());
249 void MacroAssembler::Mvn(const Register& rd, const Operand& operand) {
253 Mvn(rd, operand.immediate());
260 Register temp = temps.AcquireSameSizeAs(rd);
263 mvn(rd, Operand(temp));
267 mvn(rd, operand);
272 void MacroAssembler::Mov(const Register& rd, uint64_t imm) {
274 VIXL_ASSERT(is_uint32(imm) || is_int32(imm) || rd.Is64Bits());
291 unsigned reg_size = rd.size();
293 if (IsImmMovz(imm, reg_size) && !rd.IsSP()) {
296 movz(rd, imm);
297 } else if (IsImmMovn(imm, reg_size) && !rd.IsSP()) {
300 movn(rd, rd.Is64Bits() ? ~imm : (~imm & kWRegMask));
303 VIXL_ASSERT(!rd.IsZero());
304 LogicalImmediate(rd, AppropriateZeroRegFor(rd), n, imm_s, imm_r, ORR);
324 Register temp = rd.IsSP() ? temps.AcquireSameSizeAs(rd) : rd;
351 if (rd.IsSP()) {
352 mov(rd, temp);
434 void MacroAssembler::Csel(const Register& rd,
439 VIXL_ASSERT(!rd.IsZero());
448 csel(rd, rn, zr, cond);
450 csinc(rd, rn, zr, cond);
452 csinv(rd, rn, zr, cond);
457 csel(rd, rn, temp, cond);
461 csel(rd, rn, operand.reg(), cond);
467 csel(rd, rn, temp, cond);
472 void MacroAssembler::Add(const Register& rd,
477 AddSubMacro(rd, rn, -operand.immediate(), LeaveFlags, SUB);
479 AddSubMacro(rd, rn, operand, LeaveFlags, ADD);
484 void MacroAssembler::Adds(const Register& rd,
489 AddSubMacro(rd, rn, -operand.immediate(), SetFlags, SUB);
491 AddSubMacro(rd, rn, operand, SetFlags, ADD);
496 void MacroAssembler::Sub(const Register& rd,
501 AddSubMacro(rd, rn, -operand.immediate(), LeaveFlags, ADD);
503 AddSubMacro(rd, rn, operand, LeaveFlags, SUB);
508 void MacroAssembler::Subs(const Register& rd,
513 AddSubMacro(rd, rn, -operand.immediate(), SetFlags, ADD);
515 AddSubMacro(rd, rn, operand, SetFlags, SUB);
582 void MacroAssembler::Neg(const Register& rd,
586 Mov(rd, -operand.immediate());
588 Sub(rd, AppropriateZeroRegFor(rd), operand);
593 void MacroAssembler::Negs(const Register& rd,
596 Subs(rd, AppropriateZeroRegFor(rd), operand);
600 void MacroAssembler::AddSubMacro(const Register& rd,
605 if (operand.IsZero() && rd.Is(rn) && rd.Is64Bits() && rn.Is64Bits() &&
617 AddSub(rd, rn, temp, S, op);
619 AddSub(rd, rn, operand, S, op);
624 void MacroAssembler::Adc(const Register& rd,
628 AddSubWithCarryMacro(rd, rn, operand, LeaveFlags, ADC);
632 void MacroAssembler::Adcs(const Register& rd,
636 AddSubWithCarryMacro(rd, rn, operand, SetFlags, ADC);
640 void MacroAssembler::Sbc(const Register& rd,
644 AddSubWithCarryMacro(rd, rn, operand, LeaveFlags, SBC);
648 void MacroAssembler::Sbcs(const Register& rd,
652 AddSubWithCarryMacro(rd, rn, operand, SetFlags, SBC);
656 void MacroAssembler::Ngc(const Register& rd,
659 Register zr = AppropriateZeroRegFor(rd);
660 Sbc(rd, zr, operand);
664 void MacroAssembler::Ngcs(const Register& rd,
667 Register zr = AppropriateZeroRegFor(rd);
668 Sbcs(rd, zr, operand);
672 void MacroAssembler::AddSubWithCarryMacro(const Register& rd,
677 VIXL_ASSERT(rd.size() == rn.size());
685 AddSubWithCarry(rd, rn, Operand(temp), S, op);
688 VIXL_ASSERT(operand.reg().size() == rd.size());
690 VIXL_ASSERT(is_uintn(rd.size() == kXRegSize ? kXRegSizeLog2 : kWRegSizeLog2,
695 AddSubWithCarry(rd, rn, Operand(temp), S, op);
698 VIXL_ASSERT(operand.reg().size() <= rd.size());
708 AddSubWithCarry(rd, rn, Operand(temp), S, op);
711 AddSubWithCarry(rd, rn, operand, S, op);
