1 /* define spi-uart debug constrains */ 2 /* code for MRST early printk */ 3 #ifndef _SPI_UART 4 #define _SPI_UART 5 6 #include "types.h" 7 8 #define MRST_REGBASE_SPI0 0xff128000 9 #define MRST_REGBASE_SPI1 0xff128400 10 #define MRST_REGBASE_SPI2 0xff128800 11 12 #define CTP_REGBASE_SPI0 0xff128000 13 #define CTP_REGBASE_SPI1 0xff135000 14 #define CTP_REGBASE_SPI2 0xff136000 15 16 /* HW info for MRST CLk Control Unit, one 32b reg */ 17 #define MRST_SPI_CLK_BASE 100000000 /* 100m */ 18 #define MRST_CLK_SPI0_REG 0xff11d86c 19 #define CLK_SPI_BDIV_OFFSET 0 20 #define CLK_SPI_BDIV_MASK 0x00000007 21 #define CLK_SPI_CDIV_OFFSET 9 22 #define CLK_SPI_CDIV_MASK 0x00000e00 23 #define CLK_SPI_CDIV_100M 0x0 24 #define CLK_SPI_CDIV_50M 0x1 25 #define CLK_SPI_CDIV_33M 0x2 26 #define CLK_SPI_CDIV_25M 0x3 27 #define CLK_SPI_DISABLE_OFFSET 8 28 29 struct mrst_spi_reg { 30 vu32 ctrlr0; /* control reg 0 */ 31 vu32 ctrlr1; /* control reg 1 */ 32 vu32 ssienr; /* SSI enable reg */ 33 vu32 mwcr; /* Microwire control reg */ 34 35 vu32 ser; /* slave enable reg */ 36 vu32 baudr; 37 vu32 txftlr; 38 vu32 rxftlr; 39 40 vu32 txflr; 41 vu32 rxflr; 42 vu32 sr; 43 vu32 imr; 44 45 vu32 isr; 46 vu32 risr; 47 vu32 txoicr; 48 vu32 rxoicr; 49 50 vu32 rxuicr; 51 vu32 msticr; 52 vu32 icr; 53 vu32 dmacr; 54 55 vu32 dmatdlr; 56 vu32 dmardlr; 57 vu32 idr; 58 vu32 ssi_comp_version; 59 60 vu32 dr[16]; /* 16 bits access for each 32bit space */ 61 }; 62 63 /* bit fields in CTRLR0 */ 64 #define SPI_DFS_OFFSET 0 65 #define SPI_FRF_OFFSET 4 66 #define FRF_SPI 0x0 67 #define FRF_SSP 0x1 68 #define FRF_MICROWIRE 0x2 69 #define FRF_RESV 0x3 70 #define SPI_SCPH_OFFSET 6 71 #define SPI_SCOL_OFFSET 7 72 #define SPI_TMOD_OFFSET 8 73 #define TMOD_TR 0x0 /* xmit & recv */ 74 #define TMOD_TO 0x1 /* xmit only */ 75 #define TMOD_RO 0x2 /* recv only */ 76 #define TMOD_EPROMREAD 0x3 /* eeprom read mode */ 77 78 #define SPI_SLVOE_OFFSET 10 79 #define SPI_SRL_OFFSET 11 80 #define SPI_CFS_OFFSET 12 81 82 /* bit fields in SR, 7 bits */ 83 #define SR_MASK 0x7f /* cover 7 bits */ 84 #define SR_BUSY (1 << 0) 85 #define SR_TF_NOT_FULL (1 << 1) 86 #define SR_TF_EMPT (1 << 2) 87 #define SR_RF_NOT_EMPT (1 << 3) 88 #define SR_RF_FULL (1 << 4) 89 #define SR_TX_ERR (1 << 5) 90 #define SR_DCOL (1 << 6) 91 92 /* bit fields in ISR, IMR, RISR, 7 bits */ 93 #define SPI_INT_TXEI (1 << 0) 94 #define SPI_INT_TXOI (1 << 1) 95 #define SPI_INT_RXUI (1 << 2) 96 #define SPI_INT_RXOI (1 << 3) 97 #define SPI_INT_RXFI (1 << 4) 98 #define SPI_INT_MSTI (1 << 5) 99 100 extern void bs_spi_printk(const char *str); 101 102 #endif 103
