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      1 //===-- FunctionLoweringInfo.h - Lower functions from LLVM IR to CodeGen --===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This implements routines for translating functions from LLVM IR into
     11 // Machine IR.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #ifndef LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
     16 #define LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
     17 
     18 #include "llvm/ADT/APInt.h"
     19 #include "llvm/ADT/DenseMap.h"
     20 #include "llvm/ADT/IndexedMap.h"
     21 #include "llvm/ADT/SmallPtrSet.h"
     22 #include "llvm/ADT/SmallVector.h"
     23 #include "llvm/CodeGen/MachineBasicBlock.h"
     24 #include "llvm/IR/InlineAsm.h"
     25 #include "llvm/IR/Instructions.h"
     26 #include "llvm/Target/TargetRegisterInfo.h"
     27 #include <vector>
     28 
     29 namespace llvm {
     30 
     31 class AllocaInst;
     32 class BasicBlock;
     33 class BranchProbabilityInfo;
     34 class CallInst;
     35 class Function;
     36 class GlobalVariable;
     37 class Instruction;
     38 class MachineInstr;
     39 class MachineBasicBlock;
     40 class MachineFunction;
     41 class MachineModuleInfo;
     42 class MachineRegisterInfo;
     43 class SelectionDAG;
     44 class MVT;
     45 class TargetLowering;
     46 class Value;
     47 
     48 //===--------------------------------------------------------------------===//
     49 /// FunctionLoweringInfo - This contains information that is global to a
     50 /// function that is used when lowering a region of the function.
     51 ///
     52 class FunctionLoweringInfo {
     53   const TargetMachine &TM;
     54 public:
     55   const Function *Fn;
     56   MachineFunction *MF;
     57   MachineRegisterInfo *RegInfo;
     58   BranchProbabilityInfo *BPI;
     59   /// CanLowerReturn - true iff the function's return value can be lowered to
     60   /// registers.
     61   bool CanLowerReturn;
     62 
     63   /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
     64   /// allocated to hold a pointer to the hidden sret parameter.
     65   unsigned DemoteRegister;
     66 
     67   /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
     68   DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap;
     69 
     70   /// ValueMap - Since we emit code for the function a basic block at a time,
     71   /// we must remember which virtual registers hold the values for
     72   /// cross-basic-block values.
     73   DenseMap<const Value*, unsigned> ValueMap;
     74 
     75   /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
     76   /// the entry block.  This allows the allocas to be efficiently referenced
     77   /// anywhere in the function.
     78   DenseMap<const AllocaInst*, int> StaticAllocaMap;
     79 
     80   /// ByValArgFrameIndexMap - Keep track of frame indices for byval arguments.
     81   DenseMap<const Argument*, int> ByValArgFrameIndexMap;
     82 
     83   /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for
     84   /// function arguments that are inserted after scheduling is completed.
     85   SmallVector<MachineInstr*, 8> ArgDbgValues;
     86 
     87   /// RegFixups - Registers which need to be replaced after isel is done.
     88   DenseMap<unsigned, unsigned> RegFixups;
     89 
     90   /// MBB - The current block.
     91   MachineBasicBlock *MBB;
     92 
     93   /// MBB - The current insert position inside the current block.
     94   MachineBasicBlock::iterator InsertPt;
     95 
     96 #ifndef NDEBUG
     97   SmallPtrSet<const Instruction *, 8> CatchInfoLost;
     98   SmallPtrSet<const Instruction *, 8> CatchInfoFound;
     99 #endif
    100 
    101   struct LiveOutInfo {
    102     unsigned NumSignBits : 31;
    103     bool IsValid : 1;
    104     APInt KnownOne, KnownZero;
    105     LiveOutInfo() : NumSignBits(0), IsValid(true), KnownOne(1, 0),
    106                     KnownZero(1, 0) {}
    107   };
    108 
    109   /// VisitedBBs - The set of basic blocks visited thus far by instruction
    110   /// selection.
    111   SmallPtrSet<const BasicBlock*, 4> VisitedBBs;
    112 
    113   /// PHINodesToUpdate - A list of phi instructions whose operand list will
    114   /// be updated after processing the current basic block.
    115   /// TODO: This isn't per-function state, it's per-basic-block state. But
    116   /// there's no other convenient place for it to live right now.
    117   std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
    118 
    119   /// If the current MBB is a landing pad, the exception pointer and exception
    120   /// selector registers are copied into these virtual registers by
    121   /// SelectionDAGISel::PrepareEHLandingPad().
    122   unsigned ExceptionPointerVirtReg, ExceptionSelectorVirtReg;
    123 
    124   explicit FunctionLoweringInfo(const TargetMachine &TM) : TM(TM) {}
    125 
    126   /// set - Initialize this FunctionLoweringInfo with the given Function
    127   /// and its associated MachineFunction.
    128   ///
    129   void set(const Function &Fn, MachineFunction &MF, SelectionDAG *DAG);
    130 
    131   /// clear - Clear out all the function-specific state. This returns this
    132   /// FunctionLoweringInfo to an empty state, ready to be used for a
    133   /// different function.
    134   void clear();
    135 
    136   /// isExportedInst - Return true if the specified value is an instruction
    137   /// exported from its block.
    138   bool isExportedInst(const Value *V) {
    139     return ValueMap.count(V);
    140   }
    141 
    142   unsigned CreateReg(MVT VT);
    143 
    144   unsigned CreateRegs(Type *Ty);
    145 
    146   unsigned InitializeRegForValue(const Value *V) {
    147     unsigned &R = ValueMap[V];
    148     assert(R == 0 && "Already initialized this value register!");
    149     return R = CreateRegs(V->getType());
    150   }
    151 
    152   /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
    153   /// register is a PHI destination and the PHI's LiveOutInfo is not valid.
    154   const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) {
    155     if (!LiveOutRegInfo.inBounds(Reg))
    156       return nullptr;
    157 
    158     const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
    159     if (!LOI->IsValid)
    160       return nullptr;
    161 
    162     return LOI;
    163   }
    164 
    165   /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
    166   /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
    167   /// the register's LiveOutInfo is for a smaller bit width, it is extended to
    168   /// the larger bit width by zero extension. The bit width must be no smaller
    169   /// than the LiveOutInfo's existing bit width.
    170   const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
    171 
    172   /// AddLiveOutRegInfo - Adds LiveOutInfo for a register.
    173   void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
    174                          const APInt &KnownZero, const APInt &KnownOne) {
    175     // Only install this information if it tells us something.
    176     if (NumSignBits == 1 && KnownZero == 0 && KnownOne == 0)
    177       return;
    178 
    179     LiveOutRegInfo.grow(Reg);
    180     LiveOutInfo &LOI = LiveOutRegInfo[Reg];
    181     LOI.NumSignBits = NumSignBits;
    182     LOI.KnownOne = KnownOne;
    183     LOI.KnownZero = KnownZero;
    184   }
    185 
    186   /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
    187   /// register based on the LiveOutInfo of its operands.
    188   void ComputePHILiveOutRegInfo(const PHINode*);
    189 
    190   /// InvalidatePHILiveOutRegInfo - Invalidates a PHI's LiveOutInfo, to be
    191   /// called when a block is visited before all of its predecessors.
    192   void InvalidatePHILiveOutRegInfo(const PHINode *PN) {
    193     // PHIs with no uses have no ValueMap entry.
    194     DenseMap<const Value*, unsigned>::const_iterator It = ValueMap.find(PN);
    195     if (It == ValueMap.end())
    196       return;
    197 
    198     unsigned Reg = It->second;
    199     LiveOutRegInfo.grow(Reg);
    200     LiveOutRegInfo[Reg].IsValid = false;
    201   }
    202 
    203   /// setArgumentFrameIndex - Record frame index for the byval
    204   /// argument.
    205   void setArgumentFrameIndex(const Argument *A, int FI);
    206 
    207   /// getArgumentFrameIndex - Get frame index for the byval argument.
    208   int getArgumentFrameIndex(const Argument *A);
    209 
    210 private:
    211   /// LiveOutRegInfo - Information about live out vregs.
    212   IndexedMap<LiveOutInfo, VirtReg2IndexFunctor> LiveOutRegInfo;
    213 };
    214 
    215 /// ComputeUsesVAFloatArgument - Determine if any floating-point values are
    216 /// being passed to this variadic function, and set the MachineModuleInfo's
    217 /// usesVAFloatArgument flag if so. This flag is used to emit an undefined
    218 /// reference to _fltused on Windows, which will link in MSVCRT's
    219 /// floating-point support.
    220 void ComputeUsesVAFloatArgument(const CallInst &I, MachineModuleInfo *MMI);
    221 
    222 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
    223 /// call, and add them to the specified machine basic block.
    224 void AddCatchInfo(const CallInst &I,
    225                   MachineModuleInfo *MMI, MachineBasicBlock *MBB);
    226 
    227 /// AddLandingPadInfo - Extract the exception handling information from the
    228 /// landingpad instruction and add them to the specified machine module info.
    229 void AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,
    230                        MachineBasicBlock *MBB);
    231 
    232 } // end namespace llvm
    233 
    234 #endif
    235